參數(shù)資料
型號(hào)： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁(yè)數(shù)： 59/98頁(yè)
文件大?。?/td> 595K
代理商： PSD834F2
59/98
PSD8XXF2/3/4/5
Table 32. APDCounter Operation
SRAM Standby Mode (Battery Backup).
The
PSD8xxF2/3/4/5 supports a battery backup mode
in which the contents of the SRAM are retained in
the event of a power loss. The SRAM has Voltage
Stand-by (VSTBY, PC2) that can be connected to
an external battery. When V
CC
becomes lower
than V
STBY
then the PSD8xxF2/3/4/5 automatical-
ly connectsto Voltage Stand-by (VSTBY, PC2) as
a power source to the SRAM. The SRAM Standby
Current (I
STBY
) is typically 0.5
μ
A. The SRAMdata
retention voltage is 2 V minimum. The Battery-on
Indicator (VBATON) can be routed to PC4. This
signal indicates when the V
CC
has dropped below
V
STBY
.
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input(CSI). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
Read orWrite operations involving the PSD8xxF2/
3/4/5. AHigh on PSD Chip Select Input (CSI, PD2)
disables the Flash memory, EEPROM, and
SRAM, and reduces the PSD8xxF2/3/4/5 power
consumption. However, the PLD and I/O signals
remain operational when PSD Chip Select Input
(CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD8xxF2/3/4/5 that you are
using. See the timing parameter t
SLQV
in Table 60
or Table 61.
Input Clock
The PSD8xxF2/3/4/5 provides the option to turn
off CLKIN (PD1)to the PLD to saveAC power con-
sumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting bits 4 or 5
to a 1 in PMMR0.
Input Control Signals
The PSD8xxF2/3/4/5 provides the option to turn
off the input control signals (CNTL0, CNTL1,
CNTL2, Address Strobe (ALE/AS, PD0) and DBE)
to the PLD to saveAC power consumption. These
control signals are inputs to the PLD AND Array.
During Power-down mode, or, if any of them are
not being used as part of the PLD logic equation,
these control signals should be disabled to save
AC power. They are disconnected from the PLD
AND Array by settingbits 2, 3, 4,5, and 6 to a 1 in
PMMR2.
Figure 31. Reset (RESET) Timing
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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PSD834F2-70J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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