參數(shù)資料
型號： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁數(shù)： 20/98頁
文件大小： 595K
代理商： PSD834F2
PSD8XXF2/3/4/5
20/98
Figure 5. Data Toggle Flowchart
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted toprogram a 1 to a bit that was not erased
(not erased is logic 0).
It issuggested (as withall Flash memories)to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
Erase cycle, Figure 5 still applies. the Toggle Flag
(DQ6) bit toggles until the Erase cycle is complete.
A 1 onthe Error Flag (DQ5)bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. TheMCU canread any location withinthe sec-
tor being erased to get the Toggle Flag (DQ6) bit
and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock
Bypass
(PSD833F2x,
PSD853F2x, PSD854F2x).
The Unlock Bypass
instructions allow the system to program bytes to
the Flashmemories faster than using the standard
Program instruction. The Unlock Bypass mode is
entered by first initiating two Unlockcycles. This is
PSD834F2x,
followed by a third Write cycle containing the Un-
lock Bypass code, 20h (as shown in Table 8).
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass ResetFlash in-
struction. The first cycle must contain the data
90h; thesecondcycle the data00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to Read mode.
Erasing Flash Memory
Flash Bulk Erase.
The Flash Bulk Erase instruc-
tion uses six Write operations followed by a Read
operation of the status register, as described in
Table 8. If any byte of the Bulk Erase instructionis
wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 19. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD8xxF2/3/4/5 automatically
does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase.
The Sector Erase instruc-
tion uses six Write operations, as described in Ta-
ble 8. Additional Flash Sector Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, if the
additional bytes are transmitted in a shorter time
than thetime-out period of about 100
μ
s. The input
of a new Sector Erase code restarts the time-out
period.
The status of the internal timer can be monitored
through the levelof theEraseTime-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out period is counting. If the Erase Time-
READ
DQ5 & DQ6
START
READ DQ6
FAIL
PASS
AI01370B
DQ6
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
TOGGLE
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PSD834F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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