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參數(shù)資料
| 型號： | PSD834F2 |
| 英文描述： | Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍) |
| 中文描述： | Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍） |
| 文件頁數(shù)： | 56/98頁 |
| 文件大?。?/td> | 595K |
| 代理商： | PSD834F2 |
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PSD8XXF2/3/4/5
56/98
Figure 29. APD Unit
Automatic Power-down (APD) Unit and Power-
down Mode.
The APD Unit, shown in Figure 29,
puts the PSD8xxF2/3/4/5 into Power-down mode
by monitoring the activity of Address Strobe (ALE/
AS, PD0). If the APD Unit is enabled, as soon as
activity onAddress Strobe (ALE/AS, PD0) stops, a
four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock
periods of CLKIN (PD1), Power-down (PDN) goes
High, and the PSD8xxF2/3/4/5 enters Power-
down mode, as discussed next.
Table 28. Power-down Mode’s Effect on Ports
Power-down Mode.
By default, if you enable the
APD Unit, Power-down mode is automatically en-
abled. Thedevice enters Power-down mode if Ad-
dress Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PSD8xxF2/3/4/5 is inPower-down mode:
I
If Address Strobe (ALE/AS, PD0) starts pulsing
again, the PSD8xxF2/3/4/5 returns to normal
Operating mode. The PSD8xxF2/3/4/5 also
returns to normalOperating mode if either PSD
Chip Select Input (CSI, PD2) is Low or the
Reset (RESET) input is High.
I
The MCU address/data bus is blocked from all
memory and PLDs.
I
Various signals can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not
block CLKIN (PD1) from the APD Unit.
I
All PSD8xxF2/3/4/5 memories enter Standby
mode and are drawing standby current.
However, the PLD and I/O ports blocks do not
go into Standby Mode because you don’t want
to haveto wait forthe logic and I/O to “wake-up”
before their outputs can change. See Table 28
for Power-down mode effects on PSD8xxF2/3/
4/5 ports.
I
Typical standby current is of the order of
microamperes. These standby current values
assume thatthere arenotransitions onanyPLD
input.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
SELECT
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
AI02891
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Tri-State
Peripheral I/O
Tri-State
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
| PSD834F2-70J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-70M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD834F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-90JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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