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參數(shù)資料
| 型號(hào)： | PSD834F2 |
| 英文描述： | Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍) |
| 中文描述： | Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍） |
| 文件頁數(shù)： | 5/98頁 |
| 文件大小： | 595K |
| 代理商： | PSD834F2 |
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PSD8XXF2/3/4/5
SUMMARY DESCRIPTION
The PSD8xxF2/3/4/5 family of memory systems
for microcontrollers (MCUs) brings In-System-Pro-
grammability (ISP) to Flash memory and program-
mable logic. The result is a simple and flexible
solution for embedded designs. PSD8xxF2/3/4/5
devices combine many of the peripheral functions
found in MCU based applications.
Table 1 summarizes all the devices in the
PSD834F2, PSD853F2, PSD854F2.
The CPLD in the PSD8xxF2/3/4/5 devices fea-
tures an optimized macrocell logic architecture.
The PSD macrocell was created to address the
unique requirements of embedded system de-
signs. It allows direct connection between the sys-
tem
address/data
bus,
PSD8xxF2/3/4/5 registers, to simplify communica-
tion betweenthe MCU and other supporting devic-
es.
The PSD8xxF2/3/4/5 device includes a JTAG Se-
rial Programming interface, to allow In-System
Programming (ISP) of the entire device This fea-
ture reduces development time, simplifies the
manufacturing flow, and dramatically lowers the
cost of field upgrades. Using ST’s special Fast-
JTAG programming, a design can be rapidly pro-
grammed into the PSD8xxF2/3/4/5 in as little as
seven seconds.
and
the
internal
The innovative PSD8xxF2/3/4/5 family solves key
problems faced by designers when managing dis-
crete Flash memory devices, such as:
– First-time In-System Programming (ISP)
– Complex address decoding
– Simulataneous read and write to the device.
The JTAG Serial Interface block allows In-System
Programming (ISP), and eliminates the need for
an externalBoot EPROM, oran external program-
mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
memory while the primary Flash memory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im-
plement IAP.
ST makes available a software development tool,
PSDsoft Express, that generates ANSI-C compli-
ant code for use with your target MCU. This code
allows you to manipulate the non-volatile memory
(NVM) within the PSD8xxF2/3/4/5. Code exam-
ples are also provided for:
– Flash memory IAP via the UART of the host
MCU
– Memory paging to execute code across several
PSD8xxF2/3/4/5 memory pages
– Loading,
reading,
PSD8xxF2/3/4/5 macrocells by the MCU.
and
manipulation
of
Table 1. Product Range
1
Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management
Unit (PMU), Automatic Power-down (APD)
2. SRAM may be backed up using an external battery.
Part Number
Primary Flash
Memory
(8 Sectors)
Secondary
Flash Memory
(4 Sectors)
SRAM
2
I/O Ports
Number of
Macrocells
Serial
ISP
JTAG/
ISC Port
Turbo
Mode
Input
Output
PSD813F2
1 Mbit
256 Kbit
16 Kbit
27
24
16
yes
yes
PSD813F3
1 Mbit
none
16 Kbit
27
24
16
yes
yes
PSD813F4
1 Mbit
256 Kbit
none
27
24
16
yes
yes
PSD813F5
1 Mbit
none
none
27
24
16
yes
yes
PSD833F2
1 Mbit
256 Kbit
64 Kbit
27
24
16
yes
yes
PSD834F2
2 Mbit
256 Kbit
64 Kbit
27
24
16
yes
yes
PSD853F2
1 Mbit
256 Kbit
256 Kbit
27
24
16
yes
yes
PSD854F2
2 Mbit
256 Kbit
256 Kbit
27
24
16
yes
yes
相關(guān)PDF資料 |
PDF描述 |
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| PSD835G2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲(chǔ)器可編程外設(shè)) |
| PSD835G2 | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads |
| PSD835G2V | 150V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package. Also available with 300 kRads Total Dose Rating.; Similar to IRHNA67164 with optional Total Dose Rating of 300 kRads. |
| PSD835G2-B-12B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F2-B-12B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
| PSD834F2-70J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-70M | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD834F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-90JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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