參數(shù)資料
型號(hào)： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速I(mǎi)SP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁(yè)數(shù)： 55/98頁(yè)
文件大?。?/td> 595K
代理商： PSD834F2
55/98
PSD8XXF2/3/4/5
POWER MANAGEMENT
All PSD8xxF2/3/4/5 devices offer configurable
power savingoptions. These options may be used
individually or in combinations, as follows:
I
All memory blocks in a PSD8xxF2/3/4/5
(primary and secondary Flash memory, and
SRAM) are built with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into standby
mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory “wakes up”, changes and latches its
outputs, then goes back to standby. The
designer doesnothave todoanything special to
achieve memory standby mode when no inputs
are changing—it happens automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as de-
scribed in the sections on the Power Manage-
ment Mode Registers (PMMR).
I
As with the Power Management mode, the
Automatic Power Down (APD) block allows the
PSD8xxF2/3/4/5 to reduce to stand-by current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. This feature is available
on allthe devicesof thePSD8xxF2/3/4/5 family.
The APD Unit is described in more detail in the
sections entitled “AutomaticPower-down (APD)
Unit and Power-down Mode”, on page 56.
Built inlogic monitorsthe Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain time period (MCU is asleep), the APD Unit
initiates Power-down mode (ifenabled). Once in
Power-down mode,all address/data signals are
blocked from reaching PSD8xxF2/3/4/5 memo-
ry and PLDs, and the memories are deselected
internally. This allows the memory and PLDs to
remain in standby mode even if the address/
data signals are changing state externally
(noise, other devices on the MCU bus, etc.).
Keep in mind that any unblocked PLD input sig-
nals that are changing states keeps the PLD out
of Stand-by mode, but not the memories.
I
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in standby mode even if inputs are changing.
This feature does notblock any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.
I
The PMMRs can be written by the MCU at run-
time to manage power. All PSD8xxF2/3/4/5
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 32 and Figure 33). Significant power
savings can be achieved by blocking signals
that are not used in DPLD or CPLD logic
equations.
PSD8xxF2/3/4/5 devices have a Turbo bit in
PMMR0. This bit can be set to turn the Turbo
mode off (the default is with Turbo mode turned
on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs
are changing (zero DC current). Even when in-
puts do change, significant power can be saved
at lower frequencies (AC current), compared to
when Turbo mode is on. When the Turbo mode
is on, there is a significant DC current compo-
nent and the AC component is higher.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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