參數(shù)資料
型號(hào)： PSD701S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁(yè)數(shù)： 9/104頁(yè)
文件大小： 515K
代理商： PSD701S5
PSD7XX Family
13-9
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
N/A
Address [7:4]
Address [11:8]
N/A
80C251
(Page Mode)
N/A
N/A
Address [11:8]
Address [15:12]
All Other 8-Bit
Multiplexed
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
8051XA (16-Bit)
N/A
Address [7:4]
Address [11:8]
Address [15:12]
All Other 16-Bit
Multiplexed
Address [3:0]
Address [7:4]
Address [11:8]
Address [15:12]
8-bit
Non-Multiplexed
Bus
N/A
N/A
Address [3:0]
Address [7:4]
Table 4. Latched Address Outputs
N/A = Not Applicable
*
Refer to the I/O Port Section on how to enable the Latched Address Output function.
Tables 5 and 5A show the offset address to the PSD7XX registers relative to the CSIOP
base address. The CSIOP space is the 256 bytes of address that is allocated by the user to
the internal PSD7XX registers. Some Motorola 16-bit microcontrollers, including the
M68HC16, M68302 and M683XX, have a different data byte orientation requiring separate
address offset maps.
Table 5 shows the CSIOP address offsets for all MCUs except those from Motorola in 16-bit
mode. Table 5A shows the address offsets for Motorola MCUs in 16-bit mode.
I/O Port Latched
Address Output
Assignments*
PSD7XX
Register
Description
and Address
Offset
相關(guān)PDF資料
PDF描述
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD712S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD713S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD813F4 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
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