參數(shù)資料
型號(hào)： PSD701S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁(yè)數(shù)： 71/104頁(yè)
文件大?。?/td> 515K
代理商： PSD701S5
PSD7XX Family
13-71
Watchdog Timeout Output
Once enabled, the Watchdog Timer counts down using the selected clock rate. It is
re-loaded by the PPLD output WDOG_CLR or internal reset. If the WatchDog is not
re-loaded in the time period specified in the PSDsoft Design Tool, the WatchDog times out
and generates the WDOG_RST signal to the Reset Generator and WDOG_ON to the
PPLD. The WDOG_ON signal can be used as a GPLD output to generate an interrupt to
the microcontroller.
The WDOG_RST signal can create an internal reset pulse and activate the RST_OUT pins.
The pulse width of the RST_OUT and WDOG_ON output is controlled by the Pulse
Generator.
Watchdog Timer in Power-Down Mode
When the PSD7XX enters into power down mode, the WatchDog Timer continues to
count and the operation is not affected. The RST_OUT and PPLD are still fully functional.
The PSD7XX consumes considerably less power in the power-down mode if the internal
oscillator is selected as the WatchDog clock source instead of CLKIN.
Battery Backup
The PC2 (VSTBY) pin is the input for an external battery backup voltage for the onboard
SRAM. As V
CC
falls below the value of VSTBY, an automatic internal power switchover
occurs which connects the external battery power to the onboard SRAM. The minimum
SRAM data retention voltage is 2.0V and the standby current is typically 0.5μA.
At switchover, the PC3 (CEOUT) chip select pin is automatically forced inactive and the
PC4 (VSTBYON) pin is driven active.
CEOUT can be defined in PSDsoft as a chip select for an external battery backup SRAM,
FLASH, or EEPROM. During normal operation, CEOUT is driven directly by the output of a
Micro
cell (Mcell3) to select or deselect the memory device. In battery backup mode,
CEOUT is driven high automatically to deselect the memory device. This ensures minimal
power consumption (external battery backup SRAM) and protects against inadvertent writes
during standby mode.
VSTBYON is an external indication that the PSD has switched to standby power mode. It
can be used at the designer’s discretion.
Supervisory
Function
(cont.)
相關(guān)PDF資料
PDF描述
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD712S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD713S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD813F4 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
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