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| 型號： | PSD701S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 73/104頁 |
| 文件大小： | 515K |
| 代理商： | PSD701S5 |
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PSD7XX Family
13-73
Status Register
The PSD7XX is able to generate a reset to the microcontroller from three different
sources: the WatchDog Timer, the Voltage Comparator and the Push Button reset input. In
order to determine which source causes the reset, the microcontroller needs to read the
Status Register. After the source of reset is identified, the microcontroller writes to the
Reset_Clr Register to clear the reset bits in the Status Register.
Supervisory
Function
(cont.)
Status Register
Address
:CSIOP + D8h
:CSIOP + D9h (Motorola 16 bit)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NA
Vext_en
Vtp2
Vtp1
Vtp0
Wdog
RST
RST_IN
RST
Vtp Rst
Table 40
Bit definitions:
Vtp RST
0 = V
CC
is above Vtp
1 = A Reset pulse was generated when V
CC
level had dropped below Vtp.
RST_IN
0 = RSTIN pin is driven high.
1 = A Reset pulse was generated when RSTIN pin had been driven low.
Wdog RST
0 = No WatchDog reset occurred.
1 = A Reset pulse was generated when the WatchDog Timer expired
Vtp<2:0> :
Indicates the selected internal threshold voltage reference level. A Vtp reset is issued
whenver V
CC
stays below the selected reference level.
0,0,0 – Vtpref = 4.61v
0,0,1 – Vtpref = 2.57v
0,1,0 – Vtpref = 2.76v
0,1,1 – Vtpref = 2.83v
1,0,0 – Vtpref = 3.03v
1,0,1 – Vtpref = Not used
1,1,0 – Vtpref = 4.29v
1,1,1 – Vtpref = 0, no trip point.
Vext_en:
0 – Select an internal Vtp reference level from the above table.
1 – Enable PC6 pin to serve as an external Vtp input pin. A Vtp reset is issued whenever
V
CC
stays below PC6 reference voltage level.
Reset_Clr Register
Address
:CSIOP + D6h
:CSIOP + D7h (Motorola 16 bit)
Writing 00h to this register clears the reset bits in the Status Register.
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