參數(shù)資料
型號： PSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 59/130頁
文件大?。?/td> 704K
代理商： PSD503B1
PSD5XX Famly
6-59
APDENBit
ALE Power
Down Polarity
X
ALE Status
APDCounter
0
X
Not Counting
1
X
Pulsing
Not Counting
Counting (Activates Standby
Mode After 15 Clocks)
Counting (Activates Standby
Mode After 15 Clocks)
1
1
1
1
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR CLK
ZPLD
RCLK
ZPLD
ACLK
ZPLD
TURBO
APD
ENABLE
ALE PD
Polarity
*
CMISER
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = ON
1 = ON
1 = HIGH
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
Sleep
Mode
APD CLK
1 = ON
1 = CLKIN
PMMR1
Table 17. Power Management Mode Registers (PMMR0, PMMR1)
Table 18. APDCounter Operation
Power
Management
Unit
(Cont.)
Bit 0
*
= Should be set to High (1) to operate the APD.
Bit 1
0 = ALE Power Down (PD) Polarity Low.
1 = ALE Power Down (PD) Polarity High.
Bit 2
0 = Automatic Power Down (APD) Disable.
1 = Automatic Power Down (APD) Enable.
Bit 3
0 = EPROM/SRAM CMiser is OFF.
1 = EPROM/SRAM CMiser is ON.
Bit 4
0 = ZPLD Turbo is ON. ZPLD is always ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
Bit 5
0 = ZPLD Clock Input into the Array from the CLKIN pin input is connected. Every
Clock change will Power Up the ZPLD when Turbo bit is OFF.
1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected.
Bit 6
0 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is connected.
1 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is disconnected.
Bit 7
0 = In the PSD5XX Clock Input is connected to the Timer.
1 = In the PSD5XX Clock Input is disconnected from the Timer.
Bit 0
0 = Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
function input.
1 = Automatic Power Down Unit Clock is connected to the PSD Clock
input (CLKIN).
0 = Sleep Mode Disabled.
1 = Sleep Mode Enabled.
Bit 2–7
0 = Reserved for future use, should be set to zero.
Bit 1
相關(guān)PDF資料
PDF描述
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
PSD502B1-15JI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; Similar to IRHY57Z30CM with optional Total Dose Rating of 300kRads
PSD502B1-15LI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; A IRHY57Z30CM with Standard Packaging
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD503B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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