參數(shù)資料
型號： PSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 41/130頁
文件大?。?/td> 704K
代理商： PSD503B1
PSD5XX Famly
6-41
Control Register
This register is used in both Standard MCU I/O Mode and Address Out modes. For setting
a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register.
Writing a “0” to the register is required for the Address Out mode. The register has a default
value of “0” after reset.
Drection Register
This register is used to control the direction of data flow in the I/O ports. Writing a “1” to
the corresponding bit in the register configures the port to be an output port, and a “0”
forces the port to be an input port. The I/O configuration of the port pins can be determined
by reading the Direction Register. After reset, the pins are in input mode.
Open Drain Register
This register determines whether the output pin driver of Port C or D is a CMOS driver or
an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects
an Open Drain driver.
Special Function Register
Writing a “1” bit to this register sets up the corresponding pin to operate in Special Function
Out mode.
PLD– I/ORegister
This is a read only status register. Reading a "1" indicates the corresponding pin is
configured as a PLD pin. A "0" indicates the pin is an I/O pin.
Data In Register
This register is used in the Standard MCU I/O Mode configuration to read the input pins.
Data Out Register
This register holds the output data in the Standard MCU I/O Mode. The contents of the
register can also be read.
Macrocell Out Register
This register enables the user to read the outputs of the GPLD macrocell (PA, PB, and PE
macrocells).
I/ORegister Address Ofset
The I/O Register can be accessed by the microcontroller during normal read/write bus
cycles. The address of a register is defined as:
CSIOP + register address offset
The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte
space. The register address offset lies within this 256 byte space. Tables 15 and 15a are
the address offset of the registers.
I/OPorts
(Cont.)
相關PDF資料
PDF描述
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
PSD502B1-15JI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; Similar to IRHY57Z30CM with optional Total Dose Rating of 300kRads
PSD502B1-15LI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; A IRHY57Z30CM with Standard Packaging
相關代理商/技術參數(shù)
參數(shù)描述
PSD503B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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