參數(shù)資料
型號： PSD503B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 37/130頁
文件大?。?/td> 704K
代理商： PSD503B1
PSD5XX Famly
6-37
There are 5 programmable 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These
ports all have multiple operating modes, depending on the configuration. Some of the basic
functions are providing input/output for the ZPLD, the Counter/Timer, or can be used for
standard I/O. Each port pin is individually configurable, thus enabling a single 8-bit port to
perform multiple functions. The I/O ports occupy 256 bytes of memory space as defined by
“CSIOP”. Refer to the System Configuration section for I/O register address offset.
To set up the port configuration the user is required to:
1. Define I/O port chip select (CSIOP) in the ABEL file.
2. Initialize certain port configuration registers in the user’s program and/or
3. Specify the configuration in the PSD5XX PSDsoft Software.
4. Unused input pins should be tied to V
CC
or GND.
The following is a description of the operating modes of the I/O ports. The functions of the
port registers are described in later sections.
Standard MCUI/O
The Standard MCU I/O Mode provides additional I/O capability to the microcontroller.
In this mode, the ports can perform standard I/O functions such as sensing or controlling
various external I/O devices. Operation options of this mode are as follows:
J
Configuration
1.Declare pins or signals which are used as I/O in the ABEL file (PSDsoft).
2.Set the bit or bits in the Control Register to "1".
3.
As Output Port
– Write output data to Data Out Register
– Set Direction Register to output mode
4.
As Input Port
– Set Direction Register to input mode
– Read input from Data In Register
The port remains an output or input port as long as the Direction Register is not changed.
PLDI/O
The PLD I/O mode enables the port to be configured as an input to the ZPLD, or as an
output from the GPLD macrocell. The output can be tri-stated with a control signal defined
by a product term from the ZPLD. This mode is configured by the user in the PSD5XX
PSDsoft Software, and is enabled upon power up. For a detailed description, see the
section on the ZPLD.
J
Configuration
1.Declare pins or signals in the ABEL file (PSDsoft)
2.Write logic equations in the ABEL file.
3.PSDcompiler maps the PLD function to the PSD.
I/OPorts
相關(guān)PDF資料
PDF描述
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
PSD502B1-15JI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; Similar to IRHY57Z30CM with optional Total Dose Rating of 300kRads
PSD502B1-15LI 30V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package; A IRHY57Z30CM with Standard Packaging
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD503B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD503B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*