參數(shù)資料
型號(hào)： PSD4235G2V
英文描述： -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器（3.3V電源）
文件頁(yè)數(shù)： 62/89頁(yè)
文件大小： 703K
代理商： PSD4235G2V
PSD4235G2
62/89
Input Control Signals.
The PSD provides the
option to turn off the address input (A7-A0) and in-
put control signals (CNTL0, CNTL1, CNTL2, Ad-
dress Strobe (ALE/AS, PD0) and Write Enable
High-byte (WRH/DBE, PD3)) to the PLD to save
AC power consumption. These signals are inputs
to the PLD AND Array. During Power-down mode,
or, if any of them are not being used as part of the
PLD logic equation, these control signals should
be disabled to save AC power. They are discon-
nected from the PLD AND Array by setting bits 0,
2, 3, 4, 5 and 6 to a 1 in PMMR2.
Power On Reset, Warm Reset and Power-down
Power On Reset.
Upon Power-up, the PSD re-
quires a Reset (RESET) pulse of duration t
NLNH-
PO
(minimum 1 ms) after V
CC
is steady. During
this period, the device loads internal configura-
tions, clears some of the registers and sets the
Flash memory into Operating mode. After the ris-
ing edge of Reset (RESET), the PSD remains in
the Reset mode for an additional period, t
OPR
(maximum 120 ns), before the first memory ac-
cess is allowed.
The PSD Flash memory is reset to the Read mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR/WRL, CNTL0) High, during Power On
Reset for maximum security of the data contents
and to remove the possibility of data being written
on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Flash memory Write cycle initiation
is prevented automatically when V
CC
is below V
L-
KO
.
Warm Reset.
Once the device is up and running,
the device can be reset with a pulse of a much
shorter duration, t
NLNH
(minimum 150 ns). The
same t
OPR
period is needed before the device is
operational after warm reset. Figure 34 shows the
timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset.
Ta-
ble 51 shows the I/O pin, register and PLD status
during Power On Reset, warm reset and Power-
down mode. PLD outputs are always valid during
warm reset, and they are valid in Power On Reset
once the internal PSD Configuration bits are load-
ed. This loading of PSD is completed typically long
before the V
CC
ramps up to operating level. Once
the PLD is active, the state of the outputs are de-
termined by equations specified in PSDsoft Ex-
press.
Reset of Flash Memory Erase and Program Cy-
cles.
An external Reset (RESET) also resets the
internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset
(RESET) terminates the cycle and returns the
Flash memory to the Read mode within a period of
t
NLNH-A
(minimum 25
μ
s).
Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to 0
Unchanged
Unchanged
Macrocells Flip-flop status
Cleared to 0 by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register
1
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
All other registers
Cleared to 0
Cleared to 0
Unchanged
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