參數(shù)資料
型號： PSD4235G2V
英文描述： -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器（3.3V電源）
文件頁數(shù)： 53/89頁
文件大?。?/td> 703K
代理商： PSD4235G2V
53/89
PSD4235G2
Table 41. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
Address In Mode.
For MCUs that have more
than 16 address signals, the higher addresses can
be connected to Port A, B, C, D or F, and are rout-
ed as inputs to the PLDs. The address input can
be latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is included
in the DPLD equations for the primary Flash mem-
ory, secondary Flash memory or SRAM is consid-
ered to be an address input.
Data Port Mode.
Ports F and G can be used as a
data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to
the data bus of the MCU. The general I/O func-
tions are disabled in Ports F and G if the ports are
configured as a Data Port. Data Port mode is au-
tomatically configured in PSDsoft Express when a
non-multiplexed bus MCU is selected.
Peripheral I/O Mode.
Peripheral I/O mode can
be used to interface with external 8-bit peripherals.
In this mode, all of Port F serves as a tri-state, bi-
directional data buffer for the MCU. Peripheral I/O
mode is enabled by setting bit 7 of the VM Register
to a 1. Figure 28 shows how Port A acts as a bi-
directional buffer for the MCU data bus if Peripher-
al I/O mode is enabled. An equation for PSEL0
and/or PSEL1 must be specified in PSDsoft Ex-
press. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
JTAG In-System Programming (ISP).
Port E is
JTAG compliant, and can be used for In-System
Programming (ISP). You can multiplex JTAG op-
erations with other functions on Port E because In-
System Programming (ISP) is not performed dur-
ing normal system operation. For more information
on the JTAG Port, see the section entitled “Reset
(RESET) Timing”, on page 63.
MCU Reset Mode.
Ports F and G can be config-
ured to operate in MCU Reset mode. This mode is
available when PSD is configured for the Motorola
16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Two dedicated buffers are usually
enabled during reset to drive the data bus lines to
the desired logic level.
The PSD can replace the two buffers by configur-
ing Ports F and G to operate in MCU Reset mode.
In this mode, the PSD will drive the pre-defined
logic level or data pattern on to the MCU data bus
when Reset is active and there is no ongoing bus
cycle. After reset, Ports F and G return to the nor-
mal Data Port mode.
The MCU Reset mode is enabled and configured
in PSDsoft Express. The user defines the logic lev-
el (data pattern) that will be drive out from Ports F
and G during reset.
Port Configuration Registers (PCR).
Each Port
has a set of Port Configuration Registers (PCR)
used for configuration. The contents of the regis-
ters can be accessed by the MCU through normal
read/write bus cycles at the addresses given in Ta-
ble 6. The addresses in Table 6 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, bit 0 in a register refers to bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 42, are used for setting the
Port configurations. The default Power-up state for
each register in Table 42 is 00h.
Table 42. Port Configuration Registers (PCR)
Note: 1. See Table 46 for Drive Register bit definition.
Control Register.
Any bit reset to 0 in the Control
Register sets the corresponding port pin to MCU I/
O mode, and a 1 sets it to Address Out mode. The
default mode is MCU I/O. Only Ports E, F and G
have an associated Control Register.
MCU
Port E
(PE3-PE0)
Port E
(PE7-PE4)
Port F
(PF3-PF0)
Port F
(PF7-PF4)
Port G
(PG3-PG0)
Port G
(PG7-PG4)
80C51XA
N/A
1
Address
a7-a4
N/A
Address
a7-a4
Address
a11-a8
Address
a15-a12
All Other
MCU with Multiplexed Bus
Address
a3-a0
Address
a7-a4
Address
a3-a0
Address
a7-a4
Address
a11-a8
Address
a15-a12
Register Name
Port
MCU Access
Control
E, F, G
Write/Read
Direction
A, B, C, D, E, F, G
Write/Read
Drive Select
1
A, B, C, D, E, F, G
Write/Read
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