參數(shù)資料
型號(hào)： PSD4235G2V
英文描述： -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器（3.3V電源）
文件頁(yè)數(shù)： 28/89頁(yè)
文件大?。?/td> 703K
代理商： PSD4235G2V
PSD4235G2
28/89
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 19 to Table 20.
Reset
The Reset instruction consists of one Write cycle
(see Table 29). It can also be optionally preceded
by the standard two write decoding cycles (writing
AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after:
– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device
has set the Error Flag (DQ5/DQ13) bit to 1) dur-
ing a Flash memory Program or Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal Read mode. However, if
there is an error condition (with the Error Flag
(DQ5/DQ13) bit set to 1) the Flash memory will re-
turn to the Read mode in 25
μ
s after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-go-
ing Sector Erase cycle, and returns the Flash
memory to the normal Read mode in 25
μ
s.
Reset (RESET) Pin.
A pulse on the Reset (RE-
SET) pin aborts any cycle that is in progress, and
resets the Flash memory to the Read mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25
μ
s to return to
the Read mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described on page 62) be at least 25
μ
s so that the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cy-
cle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
Memory Select Signals
The Primary Flash Memory Sector Select (FS0-
FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft Express. The following rules
apply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be larg-
er than the physical sector size.
2. Any primary Flash memory sector must
not
be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must
not
be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5. A secondary Flash memory sector
may
overlap
a primary Flash memory sector. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces
may
overlap any other memory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Figure 8. Priority Level of Memory and I/O
Components
Example.
FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
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