參數(shù)資料
型號(hào)： PSD4235G2V
英文描述： -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器（3.3V電源）
文件頁(yè)數(shù)： 54/89頁(yè)
文件大?。?/td> 703K
代理商： PSD4235G2V
PSD4235G2
54/89
Figure 28. Peripheral I/O Mode
Direction Register.
The Direction Register con-
trols the direction of data flow in the I/O Ports. Any
bit set to 1 in the Direction Register causes the
corresponding pin to be an output, and any bit set
to 0 causes it to be an input. The default mode for
all port pins is input.
Table 43. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 44. Port Pin Direction Control, Output
Enable P.T. Defined
Table 45. Port Direction Assignment Example
Figure 29 and Figure 31 show the Port Architec-
ture diagrams for Ports A/B/C and E/F/G, respec-
tively. The direction of data flow for Ports A, B, C
and F are controlled not only by the direction reg-
ister, but also by the output enable product term
from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 45. Since
Port D only contains four pins, the Direction Reg-
ister for Port D has only the four least significant
bits active.
Drive Select Register.
The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
(The slew rate is a measurement of the rise and
fall times of an output. A higher slew rate means a
faster output response and may create more elec-
trical noise. A pin operates in a high slew rate
when the corresponding bit in the Drive Register is
set to 1. The default rate is slow slew.)
Table 46 shows the Drive Register for Ports A, B,
C, D, E, F and G. It summarizes which pins can be
configured as Open Drain outputs and which pins
the slew rate can be set for.
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
AI02886
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
相關(guān)PDF資料
PDF描述
PSD4235G1-B-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235F2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G1-12B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G1-12B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
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參數(shù)描述
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4256G6V-10UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4-36 制造商:Tamura Corporation of America 功能描述:
PSD-45 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply
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