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| 型號： | PSD413A1F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個可編程輸入/輸出，通用PLD的有59個輸入） |
| 文件頁數(shù)： | 94/98頁 |
| 文件大?。?/td> | 365K |
| 代理商： | PSD413A1F |
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PSD413F Family
6-94
ADVANCE INFORMATION
Write
Operation
Status
(cont.)
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase
time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and
Toggle Bit are valid after the initial sector erase command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase
command, DQ3 may be used to determine if the sector erase timer window is still open. If
DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write
subsequent commands to the device will be ignored until the erase operation is completed
as indicated by Data Polling or Toggle Bit. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second status check, the command may not have
been accepted.
Refer to Table 4: Write Operation Status.
Data Protection
The Flash memory is designed to offer protection against accidental erasure or
programming caused by spurious system level signals that may exist during power
transitions. During power up the device automatically resets the internal state machine in
the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting
from V
CC
power-up and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, the Flash memory
locks out write cycles for V
CC
< V
LKO
. When V
CC
< V
LKO
, the command register is disabled,
all internal program/erase circuits are disabled, and the device resets to the read mode.
The Flash memory ignores all writes until V
CC
> V
LKO
. The user must ensure that the
control pins are in the correct logic state when V
CC
> V
LKO
to prevent unintentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on RDF, CSF, or WRF will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of RDF = V
IL
, CSF = V
IH
, or WRF = V
IH
. To initiate a
write cycle CSF and WRF must be a logical zero while RDF is a logical one.
Power-Up Write Inhibit
Power-up of the device with WRF = CSF = V
IL
and RDF = V
IH
will not accept commands
on the rising edge of WRF. The internal state machine is automatically reset to the read
mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD413F | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| PSD413A2F | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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