參數(shù)資料
型號(hào)： PSD413A1F
英文描述： Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁數(shù)： 2/98頁
文件大?。?/td> 365K
代理商： PSD413A1F
PSD413F Family
6-2
ADVANCE INFORMATION
Key Features
(Cont.)
J
Up to 35 I/O Ports.
Each I/O port can be individually configured by the user as standard MCU I/O ports,
PLD I/O, latched address outputs and special function I/O. Two eight-bit I/O ports
can be configured as Open Drain outputs.
J
Two separate non-volatile memory arrays.
Both 1 Mbit (128 Kbytes) of Flash memory and 64 Kbit (8 Kbytes) of Separate OTP
Boot EPROM memory are available. The Boot memory allows for continuous operation
of the MCU while the Flash memory is being written or erased. The Flash memory is
divided into four 32 Kbyte blocks that can be mapped to different address spaces.
Each block is divided into two 16 Kbyte sectors for a total of 8 sectors. Access time is
150 ns which includes address latching and DPLD decoding.
J
Embedded On-Chip Erase and Program Algorithms for the Flash Memory.
Automatically pre-programs and erases the Flash memory or any combination of
sectors. Automatically programs and verifies data at specific address locations in the
Flash memory. Data Polling and a Toggle Bit feature are included for detection of
program or erase cycle completion.
J
Low V
CC
write inhibit <= 3.2 V for the Flash Memory.
J
Sector Protection
Hardware method disables any combination of sectors from program or
erase operation.
J
Minimum 10,000 Erase/Write Cycles.
J
16 Kbit standby SRAM.
Access time is 150 ns which includes address latching and DPLD decoding. The SRAM
can be used as standby storage if standby power is supplied to the Vstby pin. Switching
between V
CC
and Vstby occurs automatically.
J
Page Logic
Page Logic is connected to the ZPLDs and enables address space expansion for
microcontrollers with limited address space capability. Up to 16 pages are available.
J
Security bit.
The security bit prevents reading the PSD configuration, ZPLD and EPROM array
contents. This inhibits copying the device on a programmer.
J
Low power operation.
The Power Management Unit (PMU) enables automatic stand-by modes in the EPROM
and ZPLDs and disables the clock to the ZPLD. Also available is an automatic power
down mode using the ALE signal.
J
68 pin plastic (J-Lead) Chip Carrier (PLDCC) package.
J
Development Tools
Supported by the PSDsoft
TM
MS-Windows
compatible development tools. Includes
PSDabel as the design entry method, an efficient Fitter, and an Address Translator
(see Figure 2).
相關(guān)PDF資料
PDF描述
PSD413F Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD413A2F Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD4235G2(中文) Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
PSD4235G2 FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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