
PSD413F Family
6-87
ADVANCE INFORMATION
Command
Definitions
(cont.)
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into
the command register. Microprocessor read cycles retrieve array data from the memory.
The device remains enabled for reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command
sequence is not required to read data. Standard microprocessor read cycles will retrieve
array data. This default value ensures that no spurious alteration of the memory content
occurs during the power transition.
Autoselect Command
Flash memory devices are intended for use in applications where the local CPU can alter
memory contents. This Flash memory contains an Autoselect command operation to
supplement the traditional programming methodology. The operation is initiated by writing
the Autoselect command sequence into the command register. While in this mode, the write
protect status of sectors can be read. Scanning the sector addresses (A14, A15F, and
A16F) while (A1, A0) = (1,0) will produce a logical “1” at device output DQ0 for a protected
sector. To terminate the operation, it is necessary to write the read/reset command
sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up
command and data write cycles. Addresses are latched on the falling edge of CSF or WRF,
whichever happens later and the data is latched on the rising edge of CSF or WRF,
whichever happens first. The rising edge of CSF or WRF (whichever happens first) begins
programming using the Embedded Program Algorithm. Upon executing the algorithm, the
system is
not required to provide further controls or timings. The device will automatically
provide adequate internally generated program pulses and verify the programmed cell
margin.
The automatic programming operation is completed when the data on DQ7 (also used as
Data Polling) is equivalent to data written to this bit at which time the device returns to the
read mode and addresses are not longer latched (see Table 4, Write Operation Status).
Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time for Data Polling operations. Data Polling must be
performed at the memory location which is being programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored.
Programming is allowed in any sequence and across sector boundaries. Beware that a data
“0” cannot be programmed back to a “1”. Attempting to do so may cause the device to
exceed programming time limits (DQ5 = 1) or result in an apparent success, according to
the data polling algorithm, but a read from reset/read mode will show that the data is still
“0”. Only erase operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Programming Algorithm using typical command strings
and bus operations.