參數(shù)資料
型號: PPC440GX-3CF400C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: Power PC 440GX Embedded Processor
中文描述: 32-BIT, 400 MHz, RISC PROCESSOR, CBGA552
封裝: 25 X 25 MM, CERAMIC, FBGA-552
文件頁數(shù): 55/93頁
文件大小: 794K
代理商: PPC440GX-3CF400C
440GX – Power PC 440GX Embedded Processor
AMCC
55
Revision 1.15 – August 30, 2007
Data Sheet
UART1_Rx
UART1 Receive data.
I/O
3.3V LVTTL
1, 4
UART1_Tx
UART1 Transmit data.
I/O
3.3V LVTTL
1, 4
UART1_DSR/CTS
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
I/O
3.3V LVTTL
1, 4
UART1_RTS/DTR
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
I/O
3.3V LVTTL
1, 4
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
I/O
3.3V LVTTL
1, 2
IIC0SDA
IIC0 Serial Data.
I/O
3.3V LVTTL
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
3.3V IIC
1, 2
IIC1SDA
IIC1 Serial Data.
I/O
3.3V IIC
1, 2
Interrupts Interface
IRQ00:10
External interrupt Requests 0 through 10.
I
3.3V LVTTL
1, 5
IRQ11:12
External interrupt Requests 11 through 12.
I
3.3V PCI
IRQ13:17
External interrupt Requests 13 through 17.
I
3.3V LVTTL
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-up
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
w/pull-up
1
TRST
Test Reset. During chip power-up, this signal must be low from the
start of V
DD
ramp-up until at least 16 SysClk cycles after V
DD
is
stable in order to initialize the JTAG controller.
I
3.3V LVTTL
w/pull-up
5
Signal Functional Description
(Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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