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Part Number 440GX
Revision 1.15 – August 30, 2007
AMCC
1
440GX
Power PC 440GX Embedded Processor
Data Sheet
Features
PowerPC
440 processor core operating up to
800MHz with 32KB I- and D-caches (with parity
checking)
On-chip 256KB SRAM configurable as L2 Code
store or Ethernet Packet store memory
Selectable processor:bus clock ratios (Refer to
the Clocking chapter in the
PPC440GX
Embedded Processor User’s Manual
for details)
Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 166MHz
(200MHz for 800MHz Rev F parts)
External Peripheral Bus (32 bits) for up to eight
devices with external mastering
DMA support for external peripherals, internal
UART and memory
PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.3
Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are SMII, GMII, RGMII, TBI and RTBI.
TCP/IP Acceleration Hardware (TAH) provided for
10/100/1000 Mbps ports that performs checksum
processing, TCP segmentation, and includes
support for jumbo frames
Programmable Interrupt Controller supports
interrupts from a variety of sources.
I2O Messaging unit for message transfer between
the CPU and PCI-X
Programmable General Purpose Timers (GPT)
Two serial ports (16750 compatible UART)
Two IIC interfaces
General Purpose I/O (GPIO) interface available
JTAG interface for board level testing
Processor can boot from PCI memory
Available in ceramic (RoHs and non-RoHS
compliant versions) and plastic packages (RoHS
and non-RoHS compliant versions).
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GX (PPC440GX)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller, configurable
256KB SRAM to be used as L2 cache or software-
controlled on-chip memory, PCI-X bus interface,
Gigabit Ethernet interfaces, TCP/IP acceleration
hardware, I2O messaging unit, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: CMOS Cu-11, 0.13
μ
m
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA) in standard
or RoHS compliant versions
Power (estimated): Less than:
4W typical @533MHz
5W typical @667MHz
6W typical @800MHz (estimated)
Supply voltages required: 3.3V, 2.5V, 1.5V