參數(shù)資料
型號: PPC440GX-3CF667C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: Power PC 440GX Embedded Processor
中文描述: 32-BIT, 667 MHz, RISC PROCESSOR, CBGA552
封裝: 25 X 25 MM, CERAMIC, FBGA-552
文件頁數(shù): 56/93頁
文件大?。?/td> 794K
代理商: PPC440GX-3CF667C
440GX – Power PC 440GX Embedded Processor
56
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
System Interface
SysClk
Main system clock input.
Clock
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
O
3.3V LVTTL
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
During chip power-up, this signal must be low from the start of V
DD
ramp-up until at least 16 SysClk cycles after V
DD
is stable.
I/O
3.3V LVTTL
1, 2
TmrClk
Processor timer external input clock.
I
3.3V LVTTL
Halt
Halt from external debugger.
I
3.3V LVTTL
1, 4
GPIO00:31
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
I/O
3.3V LVTTL
TestEn
Test Enable.
I
3.3V tolerant
2.5V CMOS
3
RcvrInh
Receiver Inhibit. Active only when TestEn is active.
I
3.3V LVTTL
RefVEn
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
I
3.3V LVTTL
w/pull-down
DrvrInh2
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
I
3.3V LVTTL
w/pull-up
2
Signal Functional Description
(Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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