參數(shù)資料
型號: PPC440GX-3CF667C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: Power PC 440GX Embedded Processor
中文描述: 32-BIT, 667 MHz, RISC PROCESSOR, CBGA552
封裝: 25 X 25 MM, CERAMIC, FBGA-552
文件頁數(shù): 75/93頁
文件大?。?/td> 794K
代理商: PPC440GX-3CF667C
440GX – Power PC 440GX Embedded Processor
AMCC
75
Revision 1.15 – August 30, 2007
Data Sheet
Internal Peripheral Interface
IIC0SClk
na
na
na
na
15.3
10.2
IIC0SDA
15.3
10.2
IIC1SClk
na
na
na
na
15.3
10.2
IIC1SDA
15.3
10.2
UARTSerClk
na
na
na
na
na
na
UART0_Rx
na
na
na
na
UART0_Tx
na
na
10.3
7.1
UART0_DCD
na
na
na
na
UART0_DSR
na
na
na
na
UART0_CTS
na
na
na
na
UART0_DTR
na
na
10.3
7.1
UART0_RI
na
na
na
na
UART0_RTS
na
na
10.3
7.1
UART1_Rx
na
na
na
na
UART1_Tx
na
na
10.3
7.1
UART1_DSR/CTS
na
na
na
na
UART1_RTS/DTR
na
na
10.3
7.1
Interrupts Interface
IRQ00:17
na
na
JTAG Interface
TDI
na
na
async
TMS
na
na
async
TDO
15.3
10.2
async
TCK
na
na
async
TRST
na
na
async
I/O Specifications—All Speeds
(Sheet 6 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O H
(minimum)
I/O L
(minimum)
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