參數(shù)資料
型號(hào): PPC440EPx-SpAfffTs
廠(chǎng)商: Applied Micro Circuits Corp.
英文描述: PowerPC 440EPx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440EPx
文件頁(yè)數(shù): 58/94頁(yè)
文件大?。?/td> 738K
代理商: PPC440EPX-SPAFFFTS
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
58
AMCC Proprietary
Revision 1.26 – October 15, 2007
DDR2/1 SDRAM Interface
BA0:2
Bank Address supporting up to eight internal banks.
O
2.5 V (1.8 V)
SDRAM-DDR
BankSel0:1
Selects up to two external DDR SDRAM banks.
O
2.5 V (1.8 V)
SDRAM-DDR
CAS
Column Address Strobe.
O
2.5 V (1.8 V)
SDRAM-DDR
ClkEn
Clock Enable.
O
2.5 V (1.8 V)
SDRAM-DDR
DM0:7
DM8
Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane.
O
2.5 V (1.8 V)
SDRAM-DDR
DQS0:7
DQS8
Byte lane data strobe.
Byte lane data strobe for ECC.
I/O
2.5 V (1.8 V)
SDRAM-DDR
ECC0:7
ECC check bits 0:7.
I/O
2.5 V (1.8 V)
SDRAM-DDR
MemAddr00:13
Memory address bus.
O
2.5 V (1.8 V)
SDRAM-DDR
MemData00:63
Memory data bus (MemData32:63 available for DDR2 only).
I/O
2.5 V (1.8 V)
SDRAM-DDR
MemClkOut
MemClkOut
Subsystem clock.
O
2.5 V (1.8 V)
SDRAM-DDR
Diff driver
MemODT0:1
DDR2 On-die termination enable (not used with DDR1).
O
2.5 V (1.8 V)
SDRAM-DDR
RAS
Row Address Strobe.
O
2.5 V (1.8 V)
SDRAM-DDR
WE
Write Enable.
O
2.5 V (1.8 V)
SDRAM-DDR
S
VREF1A:B
DDR SDRAM reference voltage 1 input.
I
Volt ref receiver
(1.25 V or 0.9 V )
S
VREF2A:B
DDR SDRAM reference voltage 2 input.
I
Volt ref driver
(1.25 V or 0.9 V )
Table 8. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
3. Must pull down (recommended value is 1 k
Ω
)
4. If not used, must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
5. If not used, must pull down (recommended value is 1 k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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