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參數(shù)資料
| 型號： | PPC440EPx-SpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 14/94頁 |
| 文件大?。?/td> | 738K |
| 代理商： | PPC440EPX-SPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
14
AMCC Proprietary
Revision 1.26 – October 15, 2007
PCI Power Management 1.1
PCI register set addressable both from on-chip processor and PCI device sides
Ability to boot from PCI bus memory
Error tracking/status
Supports initiation of transfers of the following types:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard discrete devices that
are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the
two types of DDR devices: DDR1 devices require +2.5 V and DDR2 devices require +1.8 V.
Global memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
32-bit memory interface for DDR1
32- or 64-bit memory interface for DDR2
Optional Error Checking and Correcting (ECC)
2.6-GB/s peak data rate
Two memory banks of up to 1 GB each
Maximum capacity of 2GB
Support for 128-Mb, 256-Mb, 512-Mb, and 1-Gb DDR devices, with CAS latencies of 2, 2.5, or 3
Clock frequencies from 133 MHz (266 Mbps) to 166 MHz (333 Mbps) supported
(Faster parts may be used, but must be clocked no faster than 166 MHz)
Page mode accesses (up to 16 open pages) with configurable paging policy
Programmable address mapping and timing
Software initiated self-refresh
Power management (self-refresh, suspend, sleep)
One or two chip selects
External Peripheral Bus Controller (EBC)
Features include:
Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
Up to 83 MHz operation
Burst and non-burst devices
32-bit byte-addressable data bus
Data parity
30-bit address
Peripheral Device pacing with external “Ready”
Latch data on Ready, synchronous or asynchronous
Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
External DMA Slave Support
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-STA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA400EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA533E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA533EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA667E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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