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參數(shù)資料
| 型號： | PPC440EPx-SpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 13/94頁 |
| 文件大?。?/td> | 738K |
| 代理商： | PPC440EPX-SPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
13
Secure Socket Layer (SSL) and Transport Layer Security (TLS) features
– Packet transforms
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher
Secure Real-Time Protocol (sRTP) features
– Packet transforms
– ROC removal and TAG insertion
– Variable bypass offset of header length per packet
IPsec/SSL security acceleration engine
DES, 3DES, AES, ARC-4 encryption
MD-5, SHA-1 hashing, HMAC encrypt-hash and hash-decrypt, and KASUMI
Public key acceleration for RSA, DSA and Diffie-Hellman
True or pseudo random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8 B or 16 B
– ANSI X9.17 Annex C compliant using a DES algorithm
Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands via an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
DMA controller
– Autonomous, 4-channel
– 1024-words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
KASUMI Algorithm (optional)
Key scheduling hardware
f8
and
f9
algorithm support
Automatic data padding mechanism for
f9
algorithm
KASUMI encryption and decryption modes
32-bit slave interface
Fully synchronous to PLB clock
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
PowerPC CoreConnect Bus (PLB) Specification Version 3.1
PCI Specification Version 2.2
PCI Bus Power Management Interface Specification Version 1.1
Features include:
PCI 2.2
Frequency to 66 MHz
32-bit bus
PCI Host Bus Bridge or an Adapter Device's PCI interface
Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
Support for Message Signaled Interrupts
Simple message passing capability
Asynchronous to the PLB
相關PDF資料 |
PDF描述 |
|---|---|
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-STA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA400EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA533E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA533EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA667E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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