20
Altera Corporation
Specifications
PPP Packet Processor 155 Mbps MegaCore Function (PP155) User Guide
RX Register Description
The following tables describe the registers for the receiver section of the
PP155.
RX_CTRL - Receive Control Register - ’h00
Field
Bits
Access
Function
Default
REALIGN
5
RWSC
1: Forces aligner to try new alignment
Writing a 1 to this bit (note that it always reads as 0) forces
the byte aligner to try a new alignment. This bit is ignored if
align is 0.
0
ALIGN
4
RW
0: Byte alignment disabled.
1: Byte alignment enabled.
If set, the aligner monitors the error rate to determine if the
PPP bytes are aligned to mrxdat. If data are not aligned, it
shifts the data on mrxdat to attempt to align the data. If
cleared, the PPP bytes are assumed to be aligned to
mrxdat.
0
CRCLEN
3
RW
0: CRC-CCITT mode
1: CRC-32 mode
If set, the receiver computes syndromes for received
packets using the CRC-32 polynomial, if cleared, the CRC-
CCITT 16-bit polynomial. The syndrome is always
computed and checked. Packets with bad syndromes (i.e.
with errors) are not discarded, but are counted in the
Receive FCS Error Count register and marked as erroneous
when sent to the Atlantic interface.
0
SCRAMEN
2
RW
Enable descrambling of transmit frame and descrambling of
the receive frame.
This causes the received data stream to be descrambled
using the x^43+1 scrambling polynomial. The bits are
descrambled using the most significant (higher-numbered)
bit first. All bits, including flags, the body of the packet, and
the FCS are scrambled. The descrambling process is self-
synchronizing. The descrambler is not reset by the enable
bit and will therefore synchronize the state with the received
data stream while the enable is cleared. It should, therefore,
be set to its desired value and at least 43 bits of data should
be received before turning on the enable bit.
0