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參數(shù)資料
| 型號： | PP155 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 600K |
| 代理商： | PP155 |
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14
Altera Corporation
Specifications
PPP Packet Processor 155 Mbps MegaCore Function (PP155) User Guide
TXHDLC
The TXHDLC block frames the data in the incoming transmit stream. The
following descriptions explain the principle functions of the TXHLDC
block.
Processing
The TXHDLC block inserts the FCS into the data stream for stuffing at the
end of a normal packet. The TXHDLC also inserts the abort sequence as
needed into the data stream for aborted packets, and inserts flags between
frames. It also stuffs the data and FCS octets for transparency. Stuffing is
performed 8 bits at a time (byte oriented) for high performance, and low
gate count. When enabled, it delivers octets to the Midbus interface.
FCS 16/32
The FCS is calculated using the CRC-16 or CRC-32 generating polynomial.
Scrambling
The transmit data stream is scrambled using the x
43
+1 polynomial.
Scrambling can be enabled or disabled via the Transmit Control Register.
The packet is sent to the Midbus interface for transmission.
Interfaces & Protocols
Midbus
The Midbus interface is a simple synchronous full-duplex data path bus.
The PP155 Midbus runs at 19.44 MHz over a single byte lane in each
direction. In the receive direction (RX), data is transferred from the
Midbus master to the slave (PP155). In the transmit direction (TX), data is
transferred from the slave (PP155) to the master. In each direction, the
Midbus can carry 8 bits per clock cycle. It includes midbus receive data
(
mrxdat[7:0]
) and midbus receive enable (
mrxena
) lines to indicate
valid data transfers in the RX direction, and midbus transmit data
(
mtxdat[7:0]
) and midbus transmit enable (
mtxena
) lines to indicate
valid data requests in the TX direction. Since the PP155 is a slave to the
Midbus it can work with any Midbus master.
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