參數(shù)資料
型號： PMS430E337AHFD
廠商： Texas Instruments, Inc.
英文描述： MIXED SIGNAL MICROCONTROLLERS
中文描述： 混合信號微處理器
文件頁數(shù)： 4/30頁
文件大?。?/td> 390K
代理商： PMS430E337AHFD
MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227 – OCTOBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
2
CIN
I
Input port. CIN is used as an enable for counter TPCNT1 – (Timer/Port).
COM0–3
56–53
O
Common outputs. COM0-3 are used for LCD backplanes – LCD
P0.0
9
I/O
General-purpose digital I/O
P0.1/RXD
10
I/O
General-purpose digital I/O, receive digital Input port – 8-bit Timer/Counter
P0.2/TXD
11
I/O
General-purpose digital I/O, transmit data output port – 8-bit Timer/Counter
P0.3–P0.7
12–16
I/O
Five general-purpose digital I/Os, bit 3-7
P1.0–P1.7
17–24
I/O
Eight general-purpose digital I/Os, bit 0-7
P2.0–P2.7
25–27,
31–35
I/O
Eight general-purpose digital I/Os, bit 0-7
P3.0, P3.1
36,37
I/O
Two general-purpose digital I/Os, bit 0 and bit 1
P3.2/TACLK
38
I/O
General-purpose digital I/O, clock input – Timer_A
P3.3/TA0
39
I/O
General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0
P3.4/TA1
40
I/O
General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1
P3.5/TA2
41
I/O
General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2
P3.6/TA3
42
I/O
General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3
P3.7/TA4
43
I/O
General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4
P4.0
44
I/O
General-purpose digital I/O, bit 0
P4.1
45
I/O
General-purpose digital I/O, bit 1
P4.2/STE
46
I/O
General-purpose digital I/O, slave transmit enable – USART/SPI mode
P4.3/SIMO
47
I/O
General-purpose digital I/O, slave in/master out – USART/SPI mode
P4.4/SOMI
48
I/O
General-purpose digital I/O, master in/slave out – USART/SPI mode
P4.5/UCLK
49
I/O
General-purpose digital I/O, external clock input – USART
P4.6/UTXD
50
I/O
General-purpose digital I/O, transmit data out – USART/UART mode
P4.7/URXD
51
I/O
General-purpose digital I/O, receive data in – USART/UART mode
R03
88
I
Input port of fourth positive (lowest) analog LCD level (V5) – LCD
R13
89
I
Input port of third most positive analog LCD level (V3 of V4) – LCD
R23
90
I
Input port of second most positive analog LCD level (V2) – LCD
R33
91
O
Output of most positive analog LCD level (V1) – LCD
RST/NMI
96
I
Reset input or non-maskable interrupt input port
S0
57
O
Segment line S0 – LCD
S1
58
O
Segment line S1 – LCD
S2/O2–S5/O5
59–62
O
Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD
S6/O6–S9/O9
63–66
O
Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD
S10/O10–S13/O13
67–70
O
Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD
S14/O14–S17/O17
71–74
O
Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD
S18/O18–S21/O21
75–78
O
Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD
S22/O22–S25/O25
79, 81–83
O
Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD
S26/O26–S29/O29/CMPI
84–87
O
Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29
can be used as comparator input port CMPI – Timer/Port
TCK
95
I
Test clock. TCK is the clock input port for device programming and test
TDI/VPP
93
I
Test data input. TDI/VPP is used as a data input port or input for programming voltage
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