參數(shù)資料
型號(hào): PMS430E337AHFD
廠商: Texas Instruments, Inc.
英文描述: MIXED SIGNAL MICROCONTROLLERS
中文描述: 混合信號(hào)微處理器
文件頁數(shù): 11/30頁
文件大?。?/td> 390K
代理商: PMS430E337AHFD
MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227 – OCTOBER 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
oscillator and system clock (continued)
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency which is multiplied to achieve the desired
nominal operating range:
f
(system)
(N
1)
f
(
crystal)
The crystal frequency multiplication is acheived with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long term crystal stability. The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1
μ
s the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used, which forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a PUC, the DCO
is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC.
multiplication
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well
as unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after
the operands have been loaded into the peripheral registers. No additional clock cycles are required.
digital I/O
Five eight-bit I/O ports (P0 thru P4) are implemented. Port P0 has six control registers, P1 and P2 have seven
control registers, and P3 and P4 modules have four control registers to give maximum flexibility of digital
input/output to the application:
Individual I/O bits are independently programable.
Any combination of input, output, and interrupt conditions is possible.
Interrupt processing of external events is fully implemented for all eight bits of the P0, P1, and P2 ports.
Read/write access is available to all registers by all instructions.
The seven registers are:
Input register
contains information at the pins
Output register
contains output information
Direction register
controls direction
Interrupt edge select
contains input signal change necessary for interrupt
Interrupt flags
indicates if interrupt(s) are pending
Interrupt enable
contains interrupt enable pins
Function select
determines if pin(s) used by module or port
These registers contain eight bits each with the exception of the interrupt flag register and the interrupt enable
register which are 6 bits each. The two least significant bit (LSBs) of the interrupt flag and enable registers are
located in the special function register (SFR). Five interrupt vectors are implemented, one for Port P0.0, one
for Port P0.1, one commonly used for any interrupt event on Port P0.2 to Port P0.7, one commonly used for any
interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to Port
P2.7.
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