參數(shù)資料
型號: PMS430E337AHFD
廠商: Texas Instruments, Inc.
英文描述: MIXED SIGNAL MICROCONTROLLERS
中文描述: 混合信號微處理器
文件頁數(shù): 20/30頁
文件大小: 390K
代理商: PMS430E337AHFD
MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227 – OCTOBER 1999
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
optional resistors (see Note 12)
PARAMETER
TEST CONDITIONS
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V
MIN
1.4
NOM
4.1
MAX
6.8
UNIT
k
k
R(opt1)
R(opt2)
R(opt3)
R(opt4)
R(opt5)
R(opt6)
R(opt7)
R(opt8)
R(opt9)
R(opt10)
NOTE 12: Optional resistors R(optx) for pulldown or pullup are not programmed in standard OTP/EPROM devices P/E 337.
inputs and outputs
2.1
6.2
11
4.2
12
20
k
k
k
k
k
k
k
k
6.6
19
32
Resistors, individually programmable with ROM code, all port
pins, values applicable for pull-down and pull-up
12
37
62
26
75
124
39
112
185
65
187
309
91
117
261
337
431
557
PARAMETER
CONDITIONS
VCC
MIN
NOM
MAX
UNIT
t(int)
External Interrupt timing
Port P0, P1 to P2:
External trigger signal for the interrupt
flag (see Notes 13 and 14)
3 V/5 V
1.5
cycle
t(cap)
Timer_A, Capture timing
TA0-TA4
External capture signal (see Note 15)
3 V/5 V
250
ns
f(IN)
t(H) or t(L)
t(H) or t(L)
f(XBUF)
f(TAx)
f(UCLK)
P0 1 CIN TP 0 5 UCLK SIMO SOMI
P0.1, CIN, TP 0.5, UCLK, SIMO, SOMI,
TACLK TA0-TA4
TACLK, TA0-TA4
3 V/5 V
DC
f(system)
f(system)
f(system)
f(system)
f(system)/2
f(system)
MHz
Input frequency
3 V
300
ns
5 V
300
XBUF,
CL = 20 pF
3 V/5 V
Output frequency
TA0-4, CL = 20 pF
UCLK, CL = 20 pF
XBUF,
CL = 20 pF
f(MCLK)= 1.1 MHz
f(XBUF) = f(ACLK)
f(XBUF) = f(ACLK/n)
TA0..4, CL = 20 pF
t(TAH)= t(TAL)
UCLK, C(L) = 15pF
t(UCH)= t(UCL)
3 V/5 V
DC
MHz
3 V/5 V
DC
t(Xdc)
3 V/5 V
3 V/5 V
3 V/5 V
40%
35%
50
60%
65%
t(TA)
Duty cycle of output
3 V/5 V
0
±
100
ns
t(UC)
3 V/5 V
0
±
100
ns
t(
τ)
USART: Deglitch time
See Note16
3 V
5 V
0.6
0.3
2.6
1.4
μ
s
μ
s
NOTES: 13. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The
conditions to set the flag must be met independently from this timing constraint. T(int) is defined in MCLK cycles.
14. The external interrupt signal cannot exceed the maximum input frequency (f(in))
15. The external capture signal triggers the capture event every time t(cap) is met. It may be triggered even with capture signals shorter
than t(cap). The conditions to set the flag must be met independently from this timing constraint.
16. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(
τ
) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(
τ
). The operating conditions
to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on
the URXD line.
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