參數(shù)資料
型號(hào)： PM75RSK060
廠商： POWEREX INC
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： Intellimod⑩ Module Three Phase Brake IGBT Inverter Output (75 Amperes/600 Volts)
中文描述： AC MOTOR CONTROLLER, 150 A, DMA25
封裝： POWER MODULE-25
文件頁(yè)數(shù)： 20/31頁(yè)
文件大?。?/td> 925K
代理商： PM75RSK060
Sep.1998
interface circuits, high and low side
interface circuits, or primary and
secondary sides of the isolating de-
vices can cause noise problems.
Careful layout of control power
supply and isolating circuit wiring is
necessary. The following is a list of
guidelines that should be followed
when designing interface circuits.
Figure 6.37 shows an example in-
terface circuit layout for dual type
IPMs. Figure 6.38 shows an ex-
ample interface circuit layout for a
V-Series IPMs.The shielding and
printed circuit routing techniques
used in this example are intended
to illustrate a typical application of
the layout guidelines.
INTERFACE CIRCUIT
LAYOUT GUIDELINES
I.
Maintain maximum interface
isolation. Avoid routing printed
circuit board traces from pri-
mary and secondary sides of
the isolation device near to or
above and below each other.
Any layout that increases the
primary to secondary capaci-
tance of the isolating interface
can cause noise problems.
II.
Maintain maximum control
power supply isolation. Avoid
routing printed circuit board
traces from UP, VP, WP, and N
side supplies near to each
other. High dv/dts exist be-
tween these supplies and
noise will be coupled through
parasitic capacitances.
If isolated power supplies are
derived from a common trans-
former interwinding capaci-
tance should be minimized.
III. Keep printed circuit board
traces between the interface
circuit and IPM short. Long
traces have a tendency to pick
up noise from other parts of the
circuit.
IV. Use recommended decoupling
capacitors for power supplies
and optocouplers. Fast switch-
ing IGBT power circuits gener-
ate dv/dt and di/dt noise. Every
precaution should be taken to
protect the control circuits from
coupled noise.
V.
Use shielding. Printed circuit
board shield layers are helpful
for controlling coupled dv/dt
noise. Figure 6.37 shows an
example of how the primary
and secondary sides of the iso-
lating interface can be
shielded.
VI. High speed optocouplers with
high common mode rejection
(CMR) should be used for sig-
nal input:
t
PLH
,t
PHL
< 0.8
μ
s
CMR > 10kV/
μ
s
@ V
CM
= 1500V
Appropriate optocoupler types
are HCPL 4503, HCPL 4504
(Hewlett Packard) and PS2041
(NEC). Usually high speed
optos require a 0.1
μ
F
decoupling capacitor close to
the opto.
VII. Select the control input pull-up
resistor with a low enough
value to avoid noise pick-up by
the high impedance IPM input
and with a high enough value
that the high speed
optotransistor can still pull the
IPM safely below the recom-
mended maximum V
CIN(on)
.
Figure 6.36
Isolated Interface Circuit for Dual Intelligent Power Modules
1
2
3
4
HCPL4504
0.1
μ
F
C
1
V
1
(+)
S
R
(+5)
C
IN
V
C (-)
P
F
O
V
1
(+)
S
R
(+5)
C
IN
V
C (-)
N
C1
DUAL IPM
C
I
F
O
+
6.8k
0.1
μ
F
6.8k
8
7
6
5
3
4
PC817
2
1
1
2
3
4
HCPL4504
8
7
6
5
3
4
PC817
3
2
2.2
μ
F
47
μ
F
50V
330
μ
F
50V
1
7
5
2
1
12
113-400
VDC
11
6
5
-
+
+
+
+
+
+
4
14
13
N
FO
N
IN
P
FO
P
IN
12
11
10
9
VIN
8
7
+15
0
+15
0
+15
0
+15
0
2
1
M57120L
1
2
3
4
5
1
2
3
4
5
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
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