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RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
8.5.3
WRITE DATA PIPELINE/MUX.......................................54
8.5.4
DESCRIPTOR INFORMATION CACHE........................54
8.5.5
FREE QUEUE CACHE..................................................55
8.6
PCI CONTROLLER......................................................................55
8.6.1
MASTER MACHINE ......................................................56
8.6.2
MASTER LOCAL BUS INTERFACE..............................58
8.6.3
TARGET MACHINE.......................................................59
8.6.4
CBI BUS INTERFACE ...................................................61
8.6.5
ERROR / BUS CONTROL.............................................61
8.7
TRANSMIT DMA CONTROLLER.................................................61
8.7.1
DATA STRUCTURES ....................................................62
8.7.2
TASK PRIORITIES........................................................74
8.7.3
DMA TRANSACTION CONTROLLER...........................74
8.7.4
READ DATA PIPELINE..................................................74
8.7.5
DESCRIPTOR INFORMATION CACHE........................74
8.7.6
FREE QUEUE CACHE..................................................75
8.8
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER75
8.8.1
TRANSMIT HDLC PROCESSOR..................................75
8.8.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR76
8.9
TRANSMIT CHANNEL ASSIGNER .............................................78
8.9.1
LINE INTERFACE TRANSLATOR (LIT) ........................80
8.9.2
LINE INTERFACE..........................................................80
8.9.3
PRIORITY ENCODER...................................................81
8.9.4
CHANNEL ASSIGNER ..................................................81