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RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
127
Register 0x180 – 0x188 : RCAS Links #0 to #2 Configuration
Bit
Type
Function
Default
Bit 31
to
Bit 5
Unused
XXXXXXXH
Bit 4
R/W
BSYNC
0
Bit 3
Unused
X
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of receive links #0 to #2.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding receive link.
Table 16 details this procedure. When link 4m (0 m 7) is configured for
operation in 8.192 Mbps H-MVIP mode (MODE[2:0]=”111”), data cannot be
received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and
4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation
of the RCAS256. From a channel assignment point of view in the RCAS256
(Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are
treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the
H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64
through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link
4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time-
slots 0 through 31 of link 4m+3.