
RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
301
Figure 40 – PCI Fast Back to Back
PCICLK
FRAMEB
AD[31:0]
C/BEB[3:0]
1
2
3
4
5
6
7
8
9
IRDYB
TRDYB
DEVSELB
T
Address
Data
Data
Byte En
Byte Enable
Bus Cmd
T
T
T
T
T
Address
Data
Bus Cmd
13.6 BERT Interface
The timing relationship between the receive link clock and data (RCLK[n] /
RD[n]) and the receive BERT port signals (RBCLK / RBD) is shown in Figure 41.
BERT is not supported for H-MVIP links. For non H-MVIP links, the selected
RCLK[n] is placed on RBCLK after an asynchronous delay. The selected receive
link data (RD[n]) is sampled on the rising edge of the associated RCLK[n] and
transferred to RBD on the falling edge of RBCLK.
Figure 41 – Receive BERT Port Timing
RCLK[n]
RD[n]
B1 B2 B3 B4 X B5 X X
X B6 B7 B8 B1 X
RBCLK
RBD
B1 B2 B3
B4
B5
B6 B7 B8
B1
The timing relationship between the transmit link clock and data (TCLK[n] /
TD[n]) and the transmit BERT port signals (TBCLK / TBD) is shown in Figure 42.
BERT is not supported for H-MVIP links. TCLK[n] is shown to have an arbitrary
gapping. When TCLK[n] is quiescent, TBD is ignored (X in Figure 42). The
selected TCLK[n] is buffered and placed on TBCLK. The transmit BERT data
(TBD) is sampled on the rising edge of the TBCLK and transferred to the
selected TD[n] on the falling edge of TCLK[n].