參數(shù)資料
型號(hào): PM7366
廠商: PMC-SIERRA INC
元件分類(lèi): 微控制器/微處理器
英文描述: FRAME ENGINE AND DATA LINK MANAGER
中文描述: 8 CHANNEL(S), 52M bps, SERIAL COMM CONTROLLER, PBGA256
封裝: BGA-256
文件頁(yè)數(shù): 51/286頁(yè)
文件大小: 2243K
代理商: PM7366
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RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
38
The writer and reader determine empty and full FIFO conditions using flags. Each block in the
partial packet buffer has an associated flag. The writer sets the flag after the block is written and
the reader clears the flag after the block is read. The flags are initialized (cleared) when the block
pointers are written using indirect block writes. The writer declares a channel FIFO overrun
whenever the writer tries to store data to a block with a set flag. In order to support optional
removal of the FCS from the packet data, the writer does not declare a block as filled (set the
block flag nor increment the transaction count) until the first double word of the next block in
channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares
both blocks as full at the same time. When the reader finishes processing a transaction, it
examines the first double word of the next block for the end-of-packet flag. If the first double word
of the next block contains only FCS bytes, the reader would, optionally, process next transaction
(end-of-packet) and consume the block, as it contains information not transferred to the RMAC
block.
9.4
Receive DMA Controller
The Receive DMA Controller block (RMAC) is a DMA controller which stores received packet data
in host computer memory. The RMAC is not directly connected to the host memory PCI bus.
Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC and
the host exchange information using receive packet descriptors (RPDs). The descriptor contains
the size and location of buffers in host memory and the packet status information associated with
the data in each buffer. RPDs are transferred from the RMAC to the host and vice versa using
descriptor reference queues. The RMAC maintains all the pointers for the operation of the
queues. The RMAC provides two receive packet descriptor reference (RPDR) free queues to
support small and large buffers. The RMAC acquires free buffers by reading RPDRs from the
free queues. After a packet is received, the RMAC places the associated RPDR onto a RPDR
ready queue. To minimise host bus accesses, the RMAC maintains a descriptor reference table
to store current DMA information. This table contains separate DMA information entries for up to
128 receive channels.
9.4.1
Data Structures
For packet data, the RMAC communicates with the host using Receive Packet Descriptors (RPD),
Receive Packet Descriptor References (RPDR), the Receive Packet Descriptor Reference Ready
(RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free
(RPDRF) queues.
The RMAC copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue,
and Small and Large RPDRF queues are data structures which are used to transfer host memory
data buffer information. All five data structures are manipulated by both the RMAC and the host
computer. The RPD holds the data buffer size, data buffer address, and packet status
information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR
queue and RPDRF queues allow the RMAC and the host to pass RPDRs back and forth. These
data structures are described in more detail in the following sections.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PM7366-BI 制造商:PMC 制造商全稱(chēng):PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER
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PM7367 制造商:PMC 制造商全稱(chēng):PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER