![](http://datasheet.mmic.net.cn/330000/PM7366_datasheet_16444405/PM7366_179.png)
RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
166
Register 0x320 : TMAC Descriptor Reference Free Queue Read
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R/W
TDRFQR[15]
0
Bit 14
R/W
TDRFQR[14]
0
Bit 13
R/W
TDRFQR[13]
0
Bit 12
R/W
TDRFQR[12]
0
Bit 11
R/W
TDRFQR[11]
0
Bit 10
R/W
TDRFQR[10]
0
Bit 9
R/W
TDRFQR[9]
0
Bit 8
R/W
TDRFQR[8]
0
Bit 7
R/W
TDRFQR[7]
0
Bit 6
R/W
TDRFQR[6]
0
Bit 5
R/W
TDRFQR[5]
0
Bit 4
R/W
TDRFQR[4]
0
Bit 3
R/W
TDRFQR[3]
0
Bit 2
R/W
TDRFQR[2]
0
Bit 1
R/W
TDRFQR[1]
0
Bit 0
R/W
TDRFQR[0]
0
This register provides the Transmit Descriptor Reference Free Queue read address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TDRFQR[15:0]:
The transmit packet descriptor reference (TPDR) free queue read bits (TDRFQR[15:0]) define
bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue read pointer. This
register is initialised by the host. The physical read address in the TDRF queue is the sum of
TDRFQR[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.