![](http://datasheet.mmic.net.cn/330000/PM7366_datasheet_16444405/PM7366_181.png)
RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
168
Register 0x328 :TMAC Descriptor Reference Ready Queue Start
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R/W
TDRRQS[15]
0
Bit 14
R/W
TDRRQS[14]
0
Bit 13
R/W
TDRRQS[13]
0
Bit 12
R/W
TDRRQS[12]
0
Bit 11
R/W
TDRRQS[11]
0
Bit 10
R/W
TDRRQS[10]
0
Bit 9
R/W
TDRRQS[9]
0
Bit 8
R/W
TDRRQS[8]
0
Bit 7
R/W
TDRRQS[7]
0
Bit 6
R/W
TDRRQS[6]
0
Bit 5
R/W
TDRRQS[5]
0
Bit 4
R/W
TDRRQS[4]
0
Bit 3
R/W
TDRRQS[3]
0
Bit 2
R/W
TDRRQS[2]
0
Bit 1
R/W
TDRRQS[1]
0
Bit 0
R/W
TDRRQS[0]
0
This register provides the Transmit Descriptor Reference Ready Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TDRRQS[15:0]:
The transmit packet descriptor reference (TDR) ready queue start bits (TDRRQS[15:0]) define
bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue start address. This
register is initialised by the host. The physical start address of the TDRF queue is the sum of
TDRRQS[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.