![](http://datasheet.mmic.net.cn/330000/PM5381_datasheet_16444347/PM5381_3.png)
PRELIMINARY
PMC-Sierra, Inc.
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
ii
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
R
ECEIVE
C
ELL AND
F
RAME
P
ROCESSOR
(RCFP)..............................................................................65
R
ECEIVE
S
CALABLE
D
ATA
Q
UEUE
(RXSDQ).....................................................................................70
R
ECEIVE
P
HY
I
NTERFACE
(RXPHY).................................................................................................71
T
RANSMIT
L
INE
I
NTERFACE
..........................................................................................................71
SONET/SDH T
RANSMIT
L
INE
I
NTERFACE
(STLI)..........................................................................72
T
RANSMIT
R
EGENERATOR
M
ULTIPLEXOR
P
ROCESSOR
(TRMP).....................................................72
T
RANSMIT
T
AIL
T
RACE
P
ROCESSOR
(TTTP).................................................................................75
T
RANSMIT
H
IGH
O
RDER
P
ATH
P
ROCESSOR
(THPP)......................................................................76
T
RANSMIT
C
ELL AND
F
RAME
P
ROCESSOR
(TCFP) ........................................................................76
T
RANSMIT
S
CALABLE
D
ATA
Q
UEUE
(TXSDQ) ...............................................................................79
T
RANSMIT
P
HY
I
NTERFACES
(RXPHY
AND
TXPHY) .....................................................................79
SONET/SDH B
IT
E
RROR
R
ATE
M
ONITOR
(SBER).......................................................................80
SONET/SDH A
LARM
R
EPORTING
C
ONTROLLER
(SARC) .............................................................80
SONET/SDH I
NBAND
E
RROR
R
EPORT
P
ROCESSOR
(SIRP).........................................................81
APS S
ERIAL
D
ATA
I
NTERFACE
......................................................................................................82
JTAG T
EST
A
CCESS
P
ORT
I
NTERFACE
.........................................................................................83
M
ICROPROCESSOR
I
NTERFACE
.....................................................................................................83
11
NORMAL MODE REGISTER DESCRIPTION.................................................................................97
12
OPERATION...................................................................................................................................430
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
SONET/SDH F
RAME
M
APPINGS AND
O
VERHEAD
B
YTE
U
SAGE
......................................................433
POS/HDLC D
ATA
S
TRUCTURE
......................................................................................................438
S
ETTING
ATM M
ODE OF
O
PERATION
..............................................................................................439
S
ETTING
P
ACKET
O
VER
SONET/SDH M
ODE OF
O
PERATION
.........................................................439
B
IT
E
RROR
R
ATE
M
ONITOR
............................................................................................................439
C
LOCKING
O
PERATIONS
................................................................................................................439
L
OOPBACK
O
PERATION
..................................................................................................................439
B
OARD
D
ESIGN
R
ECOMMENDATIONS
..............................................................................................440
P
OWER
S
UPPLIES
......................................................................................................................440
I
NTERFACING TO
ECL
OR
PECL D
EVICES
...................................................................................440
13
FUNCTIONAL TIMING...................................................................................................................441
13.1
13.2
13.3
13.4
13.5
S
ERIAL
L
INE
I
NTERFACE
.................................................................................................................441
ATM U
TOPIA
L
EVEL
3 S
YSTEM
I
NTERFACE
.....................................................................................441
P
ACKET
O
VER
SONET/SDH (POS) L
EVEL
3 S
YSTEM
I
NTERFACE
..................................................443
S
ECTION AND
L
INE
D
ATA
C
OMMUNICATION
C
HANNELS
.....................................................................446
S/UNI-2488 C
ONCEPTUAL
R
EGIONS
.............................................................................................446
14
TEST FEATURES DESCRIPTION.................................................................................................447
15
FUNCTIONAL TIMING...................................................................................................................448
16
ABSOLUTE MAXIMUM RATINGS ................................................................................................449
17
D.C. CHARACTERISTICS.............................................................................................................450