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參數(shù)資料
| 型號： | PM5390 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CONNECTOR |
| 中文描述： | ATM NETWORK INTERFACE, PBGA1152 |
| 封裝： | 35 X 35 MM, 2.39 MM HEIGHT, FCBGA-1152 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 100K |
| 代理商： | PM5390 |
PM5390
Advance
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
S/UNI-9953
PMC-2000181 (A2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2001
GENERAL DESCRIPTION
The S/UNI-9953 is a single chip ATM,
POS and 10 Gigabit Ethernet User-
Network Interface operating at 9953.28
Mbit/s and 10.3 Gbit/s. The S/UNI
9953 is intended for use in OC-192c
and high-density OC-48c POS/ATM
applications as well as 10 Gigabit
Ethernet WAN and LAN PHY port
cards.
FEATURES
Provides WAN Interface Sub-layer
(WIS), Physical Coding Sub-layer
(PCS), and Media Access Controller
(MAC) functionality for OC-192c rate
10 Gigabit Ethernet WAN PHY
datastream.
Provides PCS and MAC layer
functionality for 10.3 Gbit/s 10 Gigabit
Ethernet LAN PHY datastream.
Supports framing, scrambling/
descrambling and pointer processing
for the following:
STS-192c (STM-64-64c).
4 x STS-48c (4 x STM-16-16c).
STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
Supports alarm signal
insertion/detection, B1/2/3 processing
and insertion/termination of SONET
Section/Line/Path overhead bytes (or
SDH equivalents).
Provides ATM and POS payload
processing for:
STS-192c (STM-64-64c)
4 x STS-48c (4 x STM-16-16c).
STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
INTERFACES
Provides SATURN
POS-PHY
Level 4 16-bit LVDS System-side
Interface (clocked at 700 MHz
nominal).
Directly connects to optics via 16 bit by
622 MHz OIF SFI-4 (OIF99.102) or 16
bit by 622/645 MHz IEEE P802.3ae
XSBI line-side interfaces.
POS/ATM
Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT Rec. I.432.
Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
10 GIGABIT ETHERNET
Implements 10 Gigabit Ethernet WAN
and LAN PHY according the IEEE
P802.3ae standard currently under
development.
Provides standard IEEE P802.3ae 10
Gigabit Ethernet Media Access
Controller (10GMAC) for frame
verification.
Implements IEEE P802.3ae 64B/66B
Physical Coding Sub-layer (PCS).
10 GIGABIT ETHERNET MAC
Verifies frame integrity (FCS and
length checks).
Rx
Transport
O/H
Processor
APS
Rx Path
O/H
Processor
Rx Payload
Aligner
Rx 64B/
66B
Decoder
Rx Cell/
Frame
Processor
10 Gigabit
Ethernet
MAC
Rx SONET
BER
Monitor
Tx
Transport
O/H
Processor
Tx High-
Order Path
O/H
Processor
Tx 64B/66B
Encoder
Tx Cell/
Frame
Processor
10 Gigabit
Ethernet
MAC
APS
LVDS I/F
TXCLK_SRC+/-
RXCLK+/-
RXDATA+/-
TXDATA +/-
TXCLK+/-
R
R
T
T
O
I
T
T
T
T
T
D
C
A
A
W
R
I
R
POS-PHY
Level 4
Interface
Ingress
Flexible
FIFO
POS-PHY
Level 4
Interface
Egress
Flexible
FIFO
PL4 REF +/-
RDCLK +/-
RSCLK
RSTAT
TDCLK +/-
TDAT+/-
TCTL+/-
TSCLK
TSTAT
RDAT+/-
XSBI/
SFI-4
Rx
Interface
XSBI/
SFI-4
Tx
Interface
LVDS I/F
Microprocessor
JTAG
BLOCK DIAGRAM
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|---|---|
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