![](http://datasheet.mmic.net.cn/260000/PIC876_datasheet_15943118/PIC876_128.png)
PIC16F87X
DS30292B-page 128
1999 Microchip Technology Inc.
TABLE 12-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices
Power-on Reset,
Brown-out Reset
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
873
874
876
877
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ’0’,
q
= value depends on condition,
r
= reserved maintain clear.
Note 1:
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3:
See Table 12-5 for reset value for specific condition.
MCLR Resets
WDT Reset
uuuu uuuu
N/A
uuuu uuuu
0000h
000q quuu
(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 0000
0000 0000
-r-0 0--0
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
-r-0 0--0
Wake-up via WDT or
Interrupt
uuuu uuuu
N/A
uuuu uuuu
PC + 1
(2)
uuuq quuu
(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu
(1)
ruuu uuuu
(1)
uuuu uuuu
(1)
-r-u u--u
(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu uuuu
uuuu uuuu
-r-u u--u
W
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
xxxx xxxx
N/A
xxxx xxxx
0000h
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
r000 0000
0000 0000
-r-0 0--0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
-r-0 0--0
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2