參數(shù)資料
型號: PIC18LF2450T-I/SO
廠商: Microchip Technology
文件頁數(shù): 90/143頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28SOIC
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC18F2450/4450
DS39760A-page 48
Advance Information
2006 Microchip Technology Inc.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition
Program
Counter
RCON Register
STKPTR Register
SBOREN
RI
TO
PD
POR BOR STKFUL STKUNF
Power-on Reset
0000h
1
1100
0
RESET
Instruction
0000h
u(2)
0
uuuu
u
Brown-out
0000h
u(2)
1
11u0
u
MCLR during Power-Managed
Run modes
0000h
u(2)
u
1uuu
u
MCLR during Power-Managed
Idle modes and Sleep mode
0000h
u(2)
u
10uu
u
WDT Time-out during Full Power or
Power-Managed Run modes
0000h
u(2)
u
0uuu
u
MCLR during Full Power Execution
0000h
u(2)
u
uuuu
u
Stack Full Reset (STVREN = 1)
0000h
u(2)
u
uuuu
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u(2)
u
uuuu
u
1
Stack Underflow Error (not an actual
Reset, STVREN = 0)
0000h
u(2)
u
uuuu
u
1
WDT Time-out during Power-Managed
Idle or Sleep modes
PC + 2
u(2)
u
00uu
u
Interrupt Exit from
Power-Managed modes
PC + 2(1)
u(2)
u
u0uu
u
Legend: u = unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2:
Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
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