參數(shù)資料
型號: PIC18LF2450T-I/SO
廠商: Microchip Technology
文件頁數(shù): 40/143頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28SOIC
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC18F2450/4450
DS39760A-page 132
Advance Information
2006 Microchip Technology Inc.
There are 6 signals from the module to communicate
with and control an external transceiver:
VM: Input from the single-ended D- line
VP: Input from the single-ended D+ line
RCV: Input from the differential receiver
VMO: Output to the differential line driver
VPO: Output to the differential line driver
UOE: Output enable
The VPO and VMO signals are outputs from the SIE to
the external transceiver. The RCV signal is the output
from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
into a single pulse train. The VM and VP signals are
used to report conditions on the serial bus to the SIE
that can’t be captured with the RCV signal. The
combinations of states of these signals and their
interpretation are listed in Table 14-1 and Table 14-2.
REGISTER 14-2:
UCFG: USB CONFIGURATION REGISTER
R/W-0
U-0
R/W-0
UTEYE
UOEMON(1)
UPUEN(2,3)
UTRDIS(2)
FSEN(2)
PPB1
PPB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
UTEYE: USB Eye Pattern Test Enable bit
1
= Eye pattern test enabled
0
= Eye pattern test disabled
bit 6
UOEMON: USB OE Monitor Enable bit(1)
1
=UOE signal active; it indicates intervals during which the D+/D- lines are driving
0
=UOE signal inactive
bit 5
Unimplemented: Read as ‘0’
bit 4
UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1
= On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0
= On-chip pull-up disabled
bit 3
UTRDIS: On-Chip Transceiver Disable bit(2)
1
= On-chip transceiver disabled; digital transceiver interface enabled
0
= On-chip transceiver active
bit 2
FSEN: Full-Speed Enable bit(2)
1
= Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0
= Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0
PPB1:PPB0: Ping-Pong Buffers Configuration bits
11
= Enabled for all endpoints except Endpoint 0
10
= Even/Odd ping-pong buffers enabled for all endpoints
01
= Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00
= Even/Odd ping-pong buffers disabled
Note 1:
If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2:
The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3:
This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
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