參數(shù)資料
型號: PIC18LF2450T-I/SO
廠商: Microchip Technology
文件頁數(shù): 119/143頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28SOIC
標準包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: UART/USART,USB
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 10x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 75
REGISTER 6-1:
EECON1: MEMORY CONTROL REGISTER 1
U-0
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
U-0
—CFGS
FREE
WRERR(1)
WREN
WR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
CFGS: Flash Program or Configuration Select bit
1
= Access Configuration registers
0
= Access Flash program
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0
= Perform write-only
bit 3
WRERR: Flash Program Error Flag bit(1)
1
= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0
= The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1
= Allows write cycles to Flash program
0
= Inhibits write cycles to Flash program
bit 1
WR: Write Control bit
1
= Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0
= Write cycle complete
bit 0
Unimplemented: Read as ‘0’
Note 1:
When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
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