
PIC18F85J90 FAMILY
DS39770B-page 398
Preliminary
2007 Microchip Technology Inc.
PLL .............................................................................34
PWM Operation (Simplified) ....................................153
Reads from Flash Program Memory ..........................85
Resistor Ladder Configurations for M2 ....................165
Resistor Ladder Configurations for M3 ....................166
Single Comparator ...................................................275
Table Read Operation ................................................81
Table Write Operation ................................................82
Table Writes to Flash Program Memory ....................87
Timer0 in 16-Bit Mode ..............................................132
Timer0 in 8-Bit Mode ................................................132
Timer1 (16-Bit Read/Write Mode) ............................136
Timer1 (8-Bit Mode) .................................................136
Timer2 ......................................................................142
Timer3 (16-Bit Read/Write Mode) ............................144
Timer3 (8-Bit Mode) .................................................144
Watchdog Timer .......................................................289
BN ....................................................................................304
BNC ..................................................................................305
BNN ..................................................................................305
BNOV ...............................................................................306
BNZ ..................................................................................306
BOR. See Brown-out Reset.
BOV ..................................................................................309
BRA ..................................................................................307
Break Character (12-Bit) Transmit and Receive ..............243
BRG. See Baud Rate Generator.
BRGH Bit
TXSTA1 Register .....................................................233
TXSTA2 Register .....................................................252
Brown-out Reset (BOR) .....................................................47
and On-Chip Voltage Regulator ...............................291
Detecting ....................................................................47
BSF ..................................................................................307
BTFSC .............................................................................308
BTFSS ..............................................................................308
BTG ..................................................................................309
BZ .....................................................................................310
C
C Compilers
MPLAB C18 .............................................................346
MPLAB C30 .............................................................346
Calibration (A/D Converter) ..............................................271
CALL ................................................................................310
CALLW .............................................................................339
Capture (CCP Module) .....................................................150
Associated Registers ...............................................152
CCP Pin Configuration .............................................150
CCPR2H:CCPR2L Registers ...................................150
Software Interrupt ....................................................150
Timer1/Timer3 Mode Selection ................................150
Capture/Compare/PWM (CCP) ........................................147
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................148
CCPRxH Register ....................................................148
CCPRxL Register .....................................................148
Compare Mode. See Compare.
Configuration ............................................................148
Interaction of CCP1 and CCP2 for Timer Resources ....
149
Interconnect Configurations .....................................148
Clock Sources ....................................................................31
Default System Clock on Reset .................................32
Selection Using OSCCON Register ...........................32
CLRF ................................................................................311
CLRWDT ......................................................................... 311
Code Examples
16 x 16 Signed Multiply Routine ................................ 92
16 x 16 Unsigned Multiply Routine ............................ 92
8 x 8 Signed Multiply Routine .................................... 91
8 x 8 Unsigned Multiply Routine ................................ 91
Changing Between Capture Prescalers ................... 150
Computed GOTO Using an Offset Value ................... 61
Erasing a Flash Program Memory Row ..................... 86
Fast Register Stack ................................................... 61
How to Clear RAM (Bank 1) Using Indirect Addressing
74
Implementing a Real-Time Clock Using a Timer1 Inter-
rupt Service ..................................................... 139
Initializing PORTA .................................................... 110
Initializing PORTB .................................................... 112
Initializing PORTC ................................................... 115
Initializing PORTD ................................................... 118
Initializing PORTE .................................................... 120
Initializing PORTF .................................................... 122
Initializing PORTG ................................................... 125
Initializing PORTH ................................................... 127
Initializing PORTJ .................................................... 129
Loading the SSPBUF (SSPSR) Register ................. 188
Reading a Flash Program Memory Word .................. 85
Saving STATUS, WREG and BSR Registers in RAM ...
108
Writing to Flash Program Memory ............................. 88
Code Protection ............................................................... 283
COMF .............................................................................. 312
Comparator ...................................................................... 273
Analog Input Connection Considerations ................ 277
Associated Registers ............................................... 277
Configuration ........................................................... 274
Effects of a Reset .................................................... 276
Interrupts ................................................................. 276
Operation ................................................................. 275
Operation During Sleep ........................................... 276
Outputs .................................................................... 275
Reference ................................................................ 275
External Signal ................................................ 275
Internal Signal .................................................. 275
Response Time ........................................................ 275
Comparator Specifications ............................................... 364
Comparator Voltage Reference ....................................... 279
Accuracy and Error .................................................. 280
Associated Registers ............................................... 281
Configuring .............................................................. 279
Connection Considerations ...................................... 280
Effects of a Reset .................................................... 280
Operation During Sleep ........................................... 280
Compare (CCP Module) .................................................. 151
Associated Registers ............................................... 152
CCP Pin Configuration ............................................. 151
CCPR2 Register ...................................................... 151
Software Interrupt .................................................... 151
Special Event Trigger .............................. 145, 151, 270
Timer1/Timer3 Mode Selection ................................ 151
Computed GOTO ............................................................... 61
Configuration Bits ............................................................ 283
Configuration Register Protection .................................... 294