
2001 Microchip Technology Inc.
Advance Information
DS39580A-page 39
PIC18FXX20
4.0
MEMORY ORGANIZATION
There are three memory blocks in PIC18FXX20
devices. They are:
Program Memory
Data RAM
Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these blocks.
Additional detailed information for FLASH program
memory and Data EEPROM is provided in Section 5.0
and Section 7.0, respectively.
In addition to on-chip FLASH, the PIC18F8X20 devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1),
the controllers may access either internal or external
program memory exclusively, or both internal and
external memory in selected blocks. Additional infor-
mation on the External Memory Interface is provided in
Section 6.0.
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a
NOP
instruction).
The PIC18F6620 and PIC18F8620 each have
64 Kbytes of on-chip FLASH memory, while the
PIC18F6720 and PIC18F8720 have 128 Kbytes of
FLASH. This means that PIC18FX620 devices can
store internally up to 32,768 single word instructions,
and PIC18FX720 devices can store up to 65,536 single
word instructions.
The RESET vector address is at 0000h, and the inter-
rupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18F6620/8620 devices, while Figure 4-2 shows the
Program Memory Map for PIC18F6720/8720 devices.
4.1.1
PIC18F8X20 PROGRAM MEMORY
MODES
PIC18F8X20 devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip FLASH pro-
gram memory, these controllers can also address up to
2 Mbyte of external program memory through external
memory interface. There are four distinct operating
modes available to the controllers:
Microprocessor (MP)
Microprocessor with Boot Block (MPBB)
Extended Microcontroller (EMC)
Microcontroller (MC)
The program memory mode is determined by setting
the two Least Significant bits of the CONFIG3L config-
uration byte, as shown in Register 4-1. (See also
Section 23.1 for additional details on the device config-
uration bits.)
The program memory modes operate as follows:
The
Microprocessor Mode
permits access only
to external program memory; the contents of the
on-chip FLASH memory is ignored. The 21-bit
program counter permits access to a 2 MByte
linear program memory space.
The
Microprocessor with Boot Block Mode
accesses on-chip FLASH memory from
addresses 000000h to 0001FFh. Above this,
external program memory is accessed all the way
up to the 2 MByte limit. Program execution auto-
matically switches between the two memories as
required.
The
Microcontroller Mode
accesses only
on-chip FLASH memory. Attempts to read above
the physical limit of the on-chip FLASH (0FFFFh
for the PIC18F8620, 1FFFFh for the PIC18F8720)
causes a read of all ‘
0
’s (a
NOP
instruction).
The Microcontroller mode is also the only operat-
ing mode available to PIC18F6X20 devices.
The
Extended Microcontroller Mode
allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip FLASH memory; above
this, the device accesses external program mem-
ory up to the 2 MByte program space limit. As with
Boot Block mode, execution automatically
switches between the two memories as required.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 4-1.