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2001 Microchip Technology Inc.
Advance Information
DS39580A-page 349
PIC18FXX20
Master SSP I
2
C Bus Data
........................................325
Master SSP I
2
C Bus START/STOP Bits
Waveforms
.......................................................325
Repeat START Condition
........................................180
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode)
..............................174
Slave Synchronization
.............................................157
Slow Rise Time (MCLR Tied to V
DD
via
1 kOhm Resistor)
...............................................38
SPI Mode Timing (Master Mode)
.............................156
SPI Mode Timing (Slave Mode with CKE = 0)
.........158
SPI Mode Timing (Slave Mode with CKE = 1)
.........158
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
via 1 kOhm Resistor)
.........38
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
)
Case 1
................................................................37
Case 2
................................................................37
Time-out Sequence on Power-up (MCLR Tied to
V
DD
via 1 kOhm Resistor)
..................................37
Timing for Transition Between Timer1 and OSC1
(HS with PLL)
.....................................................27
Transition Between Timer1 and OSC1
(HS, XT, LP)
.......................................................26
Transition Between Timer1 and OSC1 (RC, EC)
.......27
Transition from OSC1 to Timer1 Oscillator
................26
USART
Synchronous Master Mode
Reception
.................................................203
Transmission
...........................................202
Transmission (Through TXEN)
................202
USART Asynchronous Reception
............................200
USART Asynchronous Transmission
.......................198
USART Asynchronous Transmission
(Back to Back)
..................................................198
Wake-up from SLEEP via Interrupt
..........................246
Timing Diagrams and Specifications
................................311
A/D Conversion
........................................................329
A/D Conversion Requirements
................................329
Brown-out Reset (BOR)
...........................................315
Capture/Compare/PWM (CCP)
................................317
Capture/Compare/PWM Requirements
...................317
CLKOUT and I/O
......................................................312
CLKOUT and I/O Requirements
...................... 312
,
313
Example SPI Master Mode (CKE = 0)
.....................319
Example SPI Master Mode (CKE = 1)
.....................320
Example SPI Mode Requirements (Master Mode,
CKE = 0)
..........................................................319
Example SPI Mode Requirements (Master Mode,
CKE = 1)
..........................................................320
Example SPI Mode Requirements (Slave Mode
CKE = 0)
..........................................................321
Example SPI Slave Mode (CKE = 0)
.......................321
Example SPI Slave Mode (CKE = 1)
.......................322
Example SPI Slave Mode Requirements
(CKE = 1)
.........................................................322
External Clock (All Modes except PLL)
....................311
External Clock Requirements
..................................311
I
2
C Bus Data
............................................................323
I
2
C Bus Data Requirements (Slave Mode)
..............324
I
2
C Bus START/STOP Bits
......................................323
I
2
C Bus START/STOP Bits Requirements
...............323
Master SSP I
2
C Bus Data Requirements
................326
Master SSP I
2
C Bus START/STOP Bits
Requirements
...................................................325
Oscillator Start-up Timer (OST)
............................... 315
Parallel Slave Port (PSP)
......................................... 318
Parallel Slave Port Requirements
............................ 318
PLL Clock
................................................................ 311
Power-up Timer (PWRT)
......................................... 315
Program Memory Read Diagram
............................. 313
Program Memory Write Diagram
............................. 314
Program Memory Write Requirements
.................... 314
RESET
..................................................................... 315
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements
........................................ 315
Timer0 and Timer1
.................................................. 316
Timer0 and Timer1 External Clock
Requirements
.................................................. 316
USART Synchronous Receive (Master/Slave)
........ 327
USART Synchronous Receive Requirements
......... 327
USART Synchronous Transmission
Requirements
.................................................. 327
USART SynchronousTransmission
(Master/Slave)
................................................. 327
Watchdog Timer (WDT)
........................................... 315
TRISE Register
PSPMODE Bit
...................................................107
,
124
TSTFSZ
........................................................................... 291
Two-Word Instructions
Example Cases
.......................................................... 46
TXSTA Register
BRGH Bit
................................................................. 194
U
Universal Synchronous Asynchronous Receiver
Transmitter. SeeUSART.
USART
Asynchronous Mode
................................................ 197
Associated Registers, Receive
........................ 200
Associated Registers, Transmit
....................... 198
Receiver
.......................................................... 199
Setting up 9-bit Mode with
Address Detect
........................................ 199
Transmitter
...................................................... 197
Baud Rate Generator (BRG)
................................... 194
Associated Registers
....................................... 194
Baud Rate Error, Calculating
........................... 194
Baud Rate Formula
......................................... 194
Baud Rates, Asynchronous Mode
(BRGH = 0)
.............................................. 195
Baud Rates, Asynchronous Mode
(BRGH = 1)
.............................................. 196
High Baud Rate Select (BRGH Bit)
................. 194
Sampling
.......................................................... 194
Serial Port Enable (SPEN Bit)
................................. 191
Synchronous Master Mode
...................................... 201
Associated Registers, Reception
..................... 204
Associated Registers, Transmit
....................... 201
Reception
........................................................ 203
Timing Diagram, Synchronous Receive
.......... 327
Timing Diagram, Synchronous
Transmission
........................................... 327
Transmission
................................................... 201
Synchronous Slave Mode
........................................ 205
Associated Registers, Receive
........................ 206
Associated Registers, Transmit
....................... 205
Reception
........................................................ 206
Transmission
................................................... 205