
2001 Microchip Technology Inc.
Advance Information
DS39580A-page 347
PIC18FXX20
Program Verification and Code Protection
Associated Registers
...............................................247
Configuration Register Protection
............................250
Data EEPROM Code Protection
..............................250
Memory Code Protection
.........................................248
Programming, Device Instructions
...................................251
PSP. See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PUSH
...............................................................................280
PWM (CCP Module)
.........................................................148
Associated Registers
...............................................149
CCPR1H:CCPR1L Registers
...................................148
Duty Cycle
................................................................148
Example Frequencies/Resolutions
..........................149
Output Diagram
........................................................148
Period
.......................................................................148
Setup for PWM Operation
........................................149
TMR2 to PR2 Match
........................................ 135
,
148
TMR4 to PR4 Match
................................................141
Q
Q Clock
............................................................................148
R
RAM. See Data Memory.
RC Oscillator
......................................................................22
RCALL
..............................................................................281
RCON Registers
................................................................97
RCSTA Register
SPEN Bit
..................................................................191
RE0
....................................................................................15
Register File
.......................................................................47
Registers
ADCON0 (A/D Control 0) Register
...........................207
ADCON1 (A/D Control 1) Register
...........................208
ADCON2 (A/D Control 2) Register
...........................209
CCPxCON (Capture/Compare/PWM Control)
Register
............................................................143
CMCON (Comparator Control) Register
..................217
CONFIG1H (Configuration 1 High) Register
............235
CONFIG2H (Configuration 2 High) Register
............236
CONFIG2L (Configuration 2 Low) Register
.............235
CONFIG3H (Configuration 3 High) Register
............237
CONFIG3L (Configuration 3 Low) Register
.............236
CONFIG3L (Configuration Byte) Register
..................41
CONFIG4L (Configuration 4 Low) Register
.............237
CONFIG5H (Configuration 5 High) Register
............238
CONFIG5L (Configuration 5 Low) Register
.............238
CONFIG6H (Configuration 6 High) Register
............240
CONFIG6L (Configuration 6 Low) Register
.............239
CONFIG7H (Configuration 7 High) Register
............242
CONFIG7L (Configuration 7 Low) Register
.............241
CVRCON (Comparator Voltage Reference
Control) Register
..............................................223
Device ID Register 1
................................................242
Device ID Register 2
................................................242
EECON1 (Data EEPROM Control 1)
Register
........................................................ 63
,
78
INTCON (Interrupt Control) Register
.........................85
INTCON2 (Interrupt Control 2) Register
....................86
INTCON3 (Interrupt Control 3) Register
....................87
IPR1 (Peripheral Interrupt Priority 1) Register
...........94
IPR2 (Peripheral Interrupt Priority 2) Register
...........95
IPR3 (Peripheral Interrupt Priority 3) Register
...........96
LVDCON (LVD Control) Register
.............................229
MEMCON (Memory Control) Register
.......................71
OSCCON Register
.....................................................25
PIE1 (Peripheral Interrupt Enable 1) Register
........... 91
PIE2 (Peripheral Interrupt Enable 2) Register
........... 92
PIE3 (Peripheral Interrupt Enable 3) Register
........... 93
PIR1 (Peripheral Interrupt Request 1) Registers
....... 88
PIR2 (Peripheral Interrupt Request 2) Register
......... 89
PIR3 (Peripheral Interrupt Request 3) Register
......... 90
PSPCON (Parallel Slave Port Control) Register
...... 125
RCON (Reset Control) Register
...........................59
,
97
RCON Register
.......................................................... 31
RCSTAx (Receive Status and Control)
Register
........................................................... 193
SSPCON1 (MSSP Control 1) Register
(I
2
C Mode)
....................................................... 162
SSPCON1 (MSSP Control 1) Register
(SPI Mode)
...................................................... 153
SSPCON2 (MSSP Control 2) Register
(I
2
C Mode)
...................................................... 163
SSPSTAT (MSSP Status) Register
(I
2
C Mode)
...................................................... 161
SSPSTAT (MSSP Status) Register
(SPI Mode)
...................................................... 152
STATUS Register
...................................................... 58
STKPTR (Stack Pointer) Register
............................. 43
Summary
..............................................................51
–
54
T0CON (Timer0 Control) Register
........................... 127
T1CON (Timer 1 Control) Register
.......................... 131
T2CON (Timer 2 Control) Register
.......................... 135
T3CON (Timer3 Control) Register
........................... 137
T4CON (Timer 4 Control) Register
.......................... 141
TXSTAx (Transmit Status and Control)
Register
........................................................... 192
WDTCON (Watchdog Timer Control)
Register
........................................................... 243
RESET
................................................................29
,
233
,
281
RETFIE
............................................................................ 282
RETLW
............................................................................ 282
RETURN
.......................................................................... 283
Revision History
............................................................... 337
RLCF
............................................................................... 283
RLNCF
............................................................................. 284
RRCF
............................................................................... 284
RRNCF
............................................................................ 285
S
SCI. See USART.
SCK
................................................................................. 151
SDI
................................................................................... 151
SDO
................................................................................. 151
Serial Clock, SCK
............................................................ 151
Serial Communication Interface. SeeUSART.
Serial Data In, SDI
........................................................... 151
Serial Data Out, SDO
...................................................... 151
Serial Peripheral Interface. SeeSPI.
SETF
................................................................................ 285
Slave Select Synchronization
.......................................... 157
Slave Select, SS
.............................................................. 151
SLEEP
..............................................................233
,
245
,
286
Software Simulator (MPLAB SIM)
................................... 294
Special Event Trigger. See Compare.
Special Features of the CPU
........................................... 233
Configuration Registers
....................................235
–
242
Special Function Registers
................................................ 47
Map
............................................................................ 49