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  • 參數(shù)資料
    型號: PIC18F46J50-I/PT
    廠商: Microchip Technology
    文件頁數(shù): 112/164頁
    文件大小: 0K
    描述: IC PIC MCU FLASH 64KB 44-TQFP
    產品培訓模塊: XLP Deep Sleep Mode
    PIC18 J Series MCU Overview
    PIC18F MPLAB® Starter Kit
    8-bit PIC® Microcontroller Portfolio
    標準包裝: 160
    系列: PIC® XLP™ 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 48MHz
    連通性: I²C,SPI,UART/USART,USB
    外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
    輸入/輸出數(shù): 34
    程序存儲器容量: 64KB(32K x 16)
    程序存儲器類型: 閃存
    RAM 容量: 3.8K x 8
    電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
    數(shù)據(jù)轉換器: A/D 13x10b
    振蕩器型: 內部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-TQFP
    包裝: 托盤
    產品目錄頁面: 657 (CN2011-ZH PDF)
    配用: AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
    2011 Microchip Technology Inc.
    DS39931D-page 51
    PIC18F46J50 FAMILY
    4.3
    Sleep Mode
    The power-managed Sleep mode is identical to the
    legacy Sleep mode offered in all other PIC devices. It is
    entered by clearing the IDLEN bit (the default state on
    device Reset) and executing the SLEEP instruction.
    This shuts down the selected oscillator (Figure 4-5). All
    clock source status bits are cleared.
    Entering the Sleep mode from any other mode does not
    require a clock switch. This is because no clocks are
    needed once the controller has entered Sleep mode. If
    the WDT is selected, the INTRC source will continue to
    operate. If the Timer1 oscillator is enabled, it will also
    continue to run.
    When a wake event occurs in Sleep mode (by interrupt,
    Reset or WDT time-out), the device will not be clocked
    until the clock source selected by the SCS<1:0> bits
    becomes ready (see Figure 4-6), or it will be clocked
    from the internal oscillator if either the Two-Speed
    Start-up or the FSCM are enabled (see Section 27.0
    ). In either case, the
    OSTS bit is set when the primary clock is providing the
    device clocks. The IDLEN and SCS bits are not
    affected by the wake-up.
    FIGURE 4-5:
    TRANSITION TIMING FOR ENTRY TO SLEEP MODE
    FIGURE 4-6:
    TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
    Q4
    Q3
    Q2
    OSC1
    Peripheral
    Sleep
    Program
    Q1
    Counter
    Clock
    CPU
    Clock
    PC + 2
    PC
    Q3 Q4 Q1 Q2
    OSC1
    Peripheral
    Program
    PC
    PLL Clock
    Q3 Q4
    Output
    CPU Clock
    Q1
    Q2 Q3 Q4 Q1 Q2
    Clock
    Counter
    PC + 6
    PC + 4
    Q1 Q2 Q3 Q4
    Wake Event
    Note 1:
    TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
    TOST(1)
    TPLL(1)
    OSTS Bit Set
    PC + 2
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