參數(shù)資料
型號: PIC18F46J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 101/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 44-TQFP
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
PIC18F MPLAB® Starter Kit
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
PIC18F47J13 FAMILY
DS39974A-page 460
Preliminary
2010 Microchip Technology Inc.
MULLW
Multiply Literal with W
Syntax:
MULLW
k
Operands:
0
k 255
Operation:
(W) x k
PRODH:PRODL
Status Affected:
None
Encoding:
0000
1101
kkkk
Description:
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0C4h
Before Instruction
W=
E2h
PRODH
=
?
PRODL
=
?
After Instruction
W=
E2h
PRODH
=
ADh
PRODL
=
08h
MULWF
Multiply W with f
Syntax:
MULWF
f {,a}
Operands:
0
f 255
a
[0,1]
Operation:
(W) x (f)
PRODH:PRODL
Status Affected:
None
Encoding:
0000
001a
ffff
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected. If
‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f
95 (5Fh). See
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W=
C4h
REG
=
B5h
PRODH
=
?
PRODL
=
?
After Instruction
W=
C4h
REG
=
B5h
PRODH
=
8Ah
PRODL
=
94h
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