
PIC18F1230/1330
2006 Microchip Technology Inc.
Advance Information
DS39758B-page 55
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F1230/1330)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
41, 46
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
41, 46
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL
(5)
STKUNF
(5)
0000 0000
41, 46
STKPTR
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
41, 47
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000
41, 46
PCLATH
Holding Register for PC<15:8>
0000 0000
41, 46
PCL
PC Low Byte (PC<7:0>)
0000 0000
41, 46
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
41, 68
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
41, 68
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
41, 68
TABLAT
Program Memory Table Latch
0000 0000
41, 68
PRODH
Product Register High Byte
xxxx xxxx
41, 79
PRODL
Product Register Low Byte
xxxx xxxx
41, 79
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
41, 89
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
41, 90
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
41, 91
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
41, 60
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
41, 60
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
41, 60
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
41, 60
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
41, 60
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
41, 60
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
41, 60
WREG
Working Register
xxxx xxxx
41, 48
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
41, 60
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
41, 60
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
41, 60
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
41, 60
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
41, 60
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
41, 60
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
41, 60
BSR
—
—
—
—
Bank Select Register
---- 0000
41, 51
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
42, 60
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
42, 60
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
42, 60
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
42, 60
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
42, 60
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
42, 60
FSR2L
Legend:
Note
Indirect Data Memory Address Pointer 2 Low Byte
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits =
01
; otherwise, it is disabled and
reads as ‘
0
’. See
Section 4.4 “Brown-out Reset (BOR)”
.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘
0
’. See
Section 2.6.4 “PLL in INTOSC Modes”
.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit =
0
); otherwise, RA5 reads
as ‘
0
’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘
0
’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
xxxx xxxx
42, 60
1:
2:
3:
4:
5:
6:
7: